From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6931AC43603 for ; Fri, 6 Dec 2019 15:42:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4559624670 for ; Fri, 6 Dec 2019 15:42:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726256AbfLFPmw (ORCPT ); Fri, 6 Dec 2019 10:42:52 -0500 Received: from relay1-d.mail.gandi.net ([217.70.183.193]:43107 "EHLO relay1-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726251AbfLFPmw (ORCPT ); Fri, 6 Dec 2019 10:42:52 -0500 X-Originating-IP: 91.224.148.103 Received: from localhost.localdomain (unknown [91.224.148.103]) (Authenticated sender: miquel.raynal@bootlin.com) by relay1-d.mail.gandi.net (Postfix) with ESMTPSA id 20E62240003; Fri, 6 Dec 2019 15:42:50 +0000 (UTC) From: Miquel Raynal To: Rob Herring , Mark Rutland , , Heiko Stuebner , Cc: Paul Kocialkowski , Maxime Chevallier , Thomas Petazzoni , Miquel Raynal Subject: [PATCH] arm64: dts: rockchip: Change RK809 PMIC interrupt polarity Date: Fri, 6 Dec 2019 16:42:47 +0100 Message-Id: <20191206154247.28057-1-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PMIC interrupt can be active high or active low depending on BIT(1) of the GPIO_INT_CFG pin. The default is 0x1, which means active high. Change the polarity in the device tree to reflect the default state. Without this and with the current code base, the interrupt never stops triggering while the MFD driver does not see anything to check/clear/mask so after 100000 spurious IRQs, the kernel simply desactivates the interrupt: irq 36: nobody cared (try booting with the "irqpoll" option) [...] handlers: [<(____ptrval____)>] irq_default_primary_handler threaded [<(____ptrval____)>] regmap_irq_thread Disabling IRQ #36 Signed-off-by: Miquel Raynal --- arch/arm64/boot/dts/rockchip/px30-evb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts index 869f90cbf0da..a922ea75639d 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts @@ -138,7 +138,7 @@ compatible = "rockchip,rk809"; reg = <0x20>; interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pmic_int>; rockchip,system-power-controller; -- 2.20.1