devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH 00/13] Add PCIe support to TI's J721E SoC
@ 2019-12-09  9:21 Kishon Vijay Abraham I
  2019-12-09  9:21 ` [PATCH 01/13] PCI: cadence: Remove stray "pm_runtime_put_sync()" in error path Kishon Vijay Abraham I
                   ` (12 more replies)
  0 siblings, 13 replies; 41+ messages in thread
From: Kishon Vijay Abraham I @ 2019-12-09  9:21 UTC (permalink / raw)
  To: Bjorn Helgaas, Lorenzo Pieralisi, Rob Herring, Arnd Bergmann,
	Andrew Murray
  Cc: linux-pci, devicetree, linux-kernel, linux-omap, Kishon Vijay Abraham I

TI's J721E SoC uses Cadence PCIe core to implement both RC mode
and EP mode.

The high level features are:
  *) Supports Legacy, MSI and MSI-X interrupt
  *) Supports upto GEN4 speed mode
  *) Supports SR-IOV
  *) Supports multiple physical function
  *) Ability to route all transactions via SMMU

This patch series
  *) Add support in Cadence PCIe core to be used for TI's J721E SoC
  *) Add a driver for J721E PCIe wrapper

This is a trimmed down series of the initial RFC series [1].

Changes from RFC [1]:
  *) Ability to route all transactions via SMMU is removed
  *) SR-IOV support is removed
  *) Miscellaneous improvement to endpoint core is removed

All these will be sent as smaller series.

I've also pushed the series along with device tree changes [2].

[1] -> https://lkml.org/lkml/2019/6/4/619
[2] -> https://github.com/kishon/linux-wip.git j7_pci_v1

Kishon Vijay Abraham I (13):
  PCI: cadence: Remove stray "pm_runtime_put_sync()" in error path
  linux/kernel.h: Add PTR_ALIGN_DOWN macro
  PCI: cadence: Add support to use custom read and write accessors
  PCI: cadence: Add support to start link and verify link status
  PCI: cadence: Add read and write accessors to perform only 32-bit
    accesses
  PCI: cadence: Allow pci_host_bridge to have custom pci_ops
  PCI: cadence: Add new *ops* for CPU addr fixup
  PCI: cadence: Use local management register to configure Vendor ID
  dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC
  dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC
  PCI: j721e: Add TI J721E PCIe driver
  misc: pci_endpoint_test: Add J721E in pci_device_id table
  MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe

 .../bindings/pci/ti,j721e-pci-ep.yaml         | 113 +++++
 .../bindings/pci/ti,j721e-pci-host.yaml       | 161 +++++++
 MAINTAINERS                                   |   3 +-
 drivers/misc/pci_endpoint_test.c              |   9 +
 drivers/pci/controller/cadence/Kconfig        |  23 +
 drivers/pci/controller/cadence/Makefile       |   1 +
 drivers/pci/controller/cadence/pci-j721e.c    | 430 ++++++++++++++++++
 .../pci/controller/cadence/pcie-cadence-ep.c  |  10 +-
 .../controller/cadence/pcie-cadence-host.c    |  55 ++-
 drivers/pci/controller/cadence/pcie-cadence.c |  48 +-
 drivers/pci/controller/cadence/pcie-cadence.h | 133 +++++-
 include/linux/kernel.h                        |   1 +
 12 files changed, 958 insertions(+), 29 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
 create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
 create mode 100644 drivers/pci/controller/cadence/pci-j721e.c

-- 
2.17.1


^ permalink raw reply	[flat|nested] 41+ messages in thread

end of thread, other threads:[~2019-12-24  8:04 UTC | newest]

Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-09  9:21 [PATCH 00/13] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 01/13] PCI: cadence: Remove stray "pm_runtime_put_sync()" in error path Kishon Vijay Abraham I
2019-12-16 13:45   ` Andrew Murray
2019-12-19  8:31     ` Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 02/13] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 03/13] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2019-12-16 14:07   ` Andrew Murray
2019-12-19 11:41     ` Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 04/13] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2019-12-17 11:58   ` Andrew Murray
2019-12-19 12:01     ` Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2019-12-09 21:15   ` Bjorn Helgaas
2019-12-16 14:49   ` Andrew Murray
2019-12-19 11:56     ` Kishon Vijay Abraham I
2019-12-19 12:03       ` Arnd Bergmann
2019-12-19 13:19         ` Kishon Vijay Abraham I
2019-12-19 20:16           ` Arnd Bergmann
2019-12-17 23:36   ` Bjorn Helgaas
2019-12-19 12:49     ` Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 06/13] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2019-12-17 12:32   ` Andrew Murray
2019-12-19 12:02     ` Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 07/13] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2019-12-17 12:40   ` Andrew Murray
2019-12-19 12:03     ` Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 08/13] PCI: cadence: Use local management register to configure Vendor ID Kishon Vijay Abraham I
2019-12-17 12:42   ` Andrew Murray
2019-12-19 12:12     ` Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 09/13] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2019-12-19  0:08   ` Rob Herring
2019-12-19 13:13     ` Kishon Vijay Abraham I
2019-12-24  8:06     ` Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 10/13] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2019-12-19  0:14   ` Rob Herring
2019-12-19 13:14     ` Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 11/13] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2019-12-17 14:23   ` Andrew Murray
2019-12-19 22:47   ` Bjorn Helgaas
2019-12-09  9:21 ` [PATCH 12/13] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2019-12-09  9:21 ` [PATCH 13/13] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).