From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A72AC43603 for ; Wed, 11 Dec 2019 03:28:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1C0542073B for ; Wed, 11 Dec 2019 03:28:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726874AbfLKD2O (ORCPT ); Tue, 10 Dec 2019 22:28:14 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:56887 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726687AbfLKD2O (ORCPT ); Tue, 10 Dec 2019 22:28:14 -0500 Received: from droid15-sz.amlogic.com (10.28.8.25) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.1591.10; Wed, 11 Dec 2019 11:28:41 +0800 From: Jian Hu To: Jerome Brunet , Neil Armstrong CC: Jian Hu , Kevin Hilman , Rob Herring , Martin Blumenstingl , Michael Turquette , Wolfram Sang , Mark Rutland , Jianxin Pan , , , , , Subject: [PATCH v2] arm64: dts: meson-a1: add I2C nodes Date: Wed, 11 Dec 2019 11:28:02 +0800 Message-ID: <20191211032802.83309-1-jian.hu@amlogic.com> X-Mailer: git-send-email 2.24.0 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.28.8.25] Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are four I2C controllers in A1 series, Share the same comptible with AXG. Compared to AXG, Drive strength feature is newly added in A1. This patch depends on A1 clock driver. Signed-off-by: Jian Hu --- This patch depends on A1 clock patchset at[0] Changes since v1 at [1]: -change reg length to 0x20 -assign i2c bus alias in dts file -add new feature note compared to AXG in changelog [0] https://lkml.kernel.org/r/20191206074052.15557-1-jian.hu@amlogic.com [1] https://lkml.kernel.org/r/20191202111253.94872-1-jian.hu@amlogic.com --- --- .../arm64/boot/dts/amlogic/meson-a1-ad401.dts | 4 + arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 142 ++++++++++++++++++ 2 files changed, 146 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts index 69c25c68c358..2d0457976233 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts +++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts @@ -13,6 +13,10 @@ aliases { serial0 = &uart_AO_B; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; }; chosen { diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index eab2ecd36aa8..66d5206a57de 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -117,6 +117,46 @@ }; }; + i2c0: i2c@1400 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x1400 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc_periphs CLKID_I2C_M_A>; + status = "disabled"; + }; + + i2c1: i2c@5c00 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x5c00 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc_periphs CLKID_I2C_M_B>; + status = "disabled"; + }; + + i2c2: i2c@6800 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x6800 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc_periphs CLKID_I2C_M_C>; + status = "disabled"; + }; + + i2c3: i2c@6c00 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x6c00 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc_periphs CLKID_I2C_M_D>; + status = "disabled"; + }; + uart_AO: serial@1c00 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; @@ -171,3 +211,105 @@ #clock-cells = <0>; }; }; + +&periphs_pinctrl { + i2c0_f11_pins:i2c0-f11 { + mux { + groups = "i2c0_sck_f11", + "i2c0_sda_f12"; + function = "i2c0"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_f9_pins:i2c0-f9 { + mux { + groups = "i2c0_sck_f9", + "i2c0_sda_f10"; + function = "i2c0"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_x_pins:i2c1-x { + mux { + groups = "i2c1_sck_x", + "i2c1_sda_x"; + function = "i2c1"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_a_pins:i2c1-a { + mux { + groups = "i2c1_sck_a", + "i2c1_sda_a"; + function = "i2c1"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_x0_pins:i2c2-x0 { + mux { + groups = "i2c2_sck_x0", + "i2c2_sda_x1"; + function = "i2c2"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_x15_pins:i2c2-x15 { + mux { + groups = "i2c2_sck_x15", + "i2c2_sda_x16"; + function = "i2c2"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_a4_pins:i2c2-a4 { + mux { + groups = "i2c2_sck_a4", + "i2c2_sda_a5"; + function = "i2c2"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_a8_pins:i2c2-a8 { + mux { + groups = "i2c2_sck_a8", + "i2c2_sda_a9"; + function = "i2c2"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_x_pins:i2c3-x { + mux { + groups = "i2c3_sck_x", + "i2c3_sda_x"; + function = "i2c3"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_f_pins:i2c3-f { + mux { + groups = "i2c3_sck_f", + "i2c3_sda_f"; + function = "i2c3"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; +}; -- 2.24.0