From: Kishon Vijay Abraham I <kishon@ti.com>
To: Rob Herring <robh+dt@kernel.org>,
Anil Varughese <aniljoy@cadence.com>,
Roger Quadros <rogerq@ti.com>, Jyri Sarha <jsarha@ti.com>
Cc: <devicetree@vger.kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v4 00/14] PHY: Add support for SERDES in TI's J721E SoC
Date: Mon, 16 Dec 2019 15:26:58 +0530 [thread overview]
Message-ID: <20191216095712.13266-1-kishon@ti.com> (raw)
TI's J721E SoC uses Cadence Sierra SERDES for USB, PCIe and SGMII.
TI has a wrapper named WIZ to control input signals to Sierra and
Torrent SERDES.
This patch series:
1) Add support to WIZ module present in TI's J721E SoC
2) Adapt Cadence Sierra PHY driver to be used for J721E SoC
Changes from v3:
*) Fix Rob's comments on dt bindings
-> Add properties to be added in WIZ child nodes to binding
-> Use '-' rather than '_' in node names
Changes from v2:
*) Deprecate "phy_clk" binding
*) Fix Rob's comment on dt bindings
-> Include BSD-2-Clause license identifier
-> drop "oneOf" and "items" for compatible
-> Fixed "num-lanes" to include only scalar keywords
-> Change to 32-bit address space for child nodes
*) Rename cmn_refclk/cmn_refclk1 to cmn_refclk_dig_div/
cmn_refclk1_dig_div
Changes from v1:
*) Change the dt binding Documentation of WIZ wrapper to YAML format
*) Fix an issue in Sierra while doimg rmmod
The series has also been pushed to
https://github.com/kishon/linux-wip.git j7_serdes_v4
Anil Varughese (1):
phy: cadence: Sierra: Configure both lane cdb and common cdb registers
for external SSC
Kishon Vijay Abraham I (13):
dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E
phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional
resources
phy: cadence: Sierra: Use "regmap" for read and write to Sierra
registers
phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC
phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops
phy: cadence: Sierra: Modify register macro names to be in sync with
Sierra user guide
phy: cadence: Sierra: Get reset control "array" for each link
phy: cadence: Sierra: Check for PLL lock during PHY power on
phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div
frequency to 25MHz
phy: cadence: Sierra: Use correct dev pointer in
cdns_sierra_phy_remove()
dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC
.../bindings/phy/phy-cadence-sierra.txt | 13 +-
.../bindings/phy/ti,phy-j721e-wiz.yaml | 204 ++++
drivers/phy/cadence/phy-cadence-sierra.c | 699 +++++++++++---
drivers/phy/ti/Kconfig | 15 +
drivers/phy/ti/Makefile | 1 +
drivers/phy/ti/phy-j721e-wiz.c | 898 ++++++++++++++++++
6 files changed, 1691 insertions(+), 139 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
create mode 100644 drivers/phy/ti/phy-j721e-wiz.c
--
2.17.1
next reply other threads:[~2019-12-16 9:56 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-16 9:56 Kishon Vijay Abraham I [this message]
2019-12-16 9:56 ` [PATCH v4 01/14] dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 02/14] phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 03/14] phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 04/14] phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 05/14] phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 06/14] phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 07/14] phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 08/14] phy: cadence: Sierra: Get reset control "array" for each link Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 09/14] phy: cadence: Sierra: Check for PLL lock during PHY power on Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 10/14] phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 11/14] phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 12/14] phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 13/14] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings Kishon Vijay Abraham I
2019-12-18 20:59 ` Rob Herring
2020-01-02 9:56 ` [PATCH v5 " Kishon Vijay Abraham I
2020-01-03 22:34 ` Rob Herring
2020-01-06 5:51 ` Kishon Vijay Abraham I
2020-01-13 17:59 ` Rob Herring
2020-01-14 8:06 ` Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 14/14] phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC Kishon Vijay Abraham I
2020-01-06 6:32 ` [PATCH v4 00/14] PHY: Add support for SERDES in TI's " Kishon Vijay Abraham I
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