From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFC29C00523 for ; Sat, 4 Jan 2020 00:21:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9254C222C3 for ; Sat, 4 Jan 2020 00:21:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1578097315; bh=5ckSlqosEWoVCoHBKmH8bs80ujWGzwAddQUBE/ZM/+w=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=ATZPRwvwjVlgghuGRe61WCSh3QOkhGXdv48J/+KAFxIJyJ/3KJ4wvwRSpPd1UwR3w wdskTAkVuA1HbYoWfRXyW6gR6NpUa3lSiz+lu16QRW0uZCtruoXgfNOHP8YUua8gMs T7gNOLDi4Bdjhe32kwpl6Zg82O5U6t2BHftrgxAE= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727187AbgADAVz (ORCPT ); Fri, 3 Jan 2020 19:21:55 -0500 Received: from mail-io1-f66.google.com ([209.85.166.66]:38873 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727077AbgADAVz (ORCPT ); Fri, 3 Jan 2020 19:21:55 -0500 Received: by mail-io1-f66.google.com with SMTP id v3so43125695ioj.5 for ; Fri, 03 Jan 2020 16:21:54 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=GRrMCIevFS+50QdWWWGaYeUVyp1OjoJAsbXHKCUBzfs=; b=YL3a+vxlapiVWbErvHCPziHEM0TwqFHADkMWjmxNcDvipqpTq1EWodtTG3vmNxXAeh 3NHKUtS1JdpGKS7yqEF+KokhJ1+Oj07lEpiqefPdvf78GfiFbERQEs/T/OplVRsO0GAf n3fnB0XkzF1O6H5+PWtKrwZe0cU9NQ2ZE0iSyIkkP2eKcPstJ9tVN24c7XuJYDTGgrrO megnpwQCZLoUUKccEPUMLb0MWV089STO9mvfIJRmUqD3PV5TtLz58w0FMTge0nxHW4ao y+IoGLehfTuCDAoqz043W7P+PqAikNPLzEAP9ie4ZnmsI8xJ0OI2455P8RneOMQoV8rh vMdw== X-Gm-Message-State: APjAAAUiPWaXtHnITWeoNlitfRGgJd3MxXns6LLLrOUsM066fYMjUQa3 GPMUVzfcU29nIa78h6v1uWwj5kc= X-Google-Smtp-Source: APXvYqyCMx5cIjBJloNCnASbsG8piUS3i3sdJZStqJLWlBlW3fZjJYdpcaq2Wm6AKdVROlk8svTZ1w== X-Received: by 2002:a02:a388:: with SMTP id y8mr72479917jak.70.1578097313970; Fri, 03 Jan 2020 16:21:53 -0800 (PST) Received: from rob-hp-laptop ([64.188.179.251]) by smtp.gmail.com with ESMTPSA id a7sm15247507iod.61.2020.01.03.16.21.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2020 16:21:53 -0800 (PST) Received: from rob (uid 1000) (envelope-from rob@rob-hp-laptop) id 2219a5 by rob-hp-laptop (DragonFly Mail Agent v0.11); Fri, 03 Jan 2020 17:21:52 -0700 Date: Fri, 3 Jan 2020 17:21:52 -0700 From: Rob Herring To: Remi Pommarel Cc: Kishon Vijay Abraham I , Yue Wang , Lorenzo Pieralisi , Andrew Murray , Neil Armstrong , Kevin Hilman , Martin Blumenstingl , Jerome Brunet , linux-amlogic@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 4/5] dt-bindings: PCI: meson: Update PCIE bindings documentation Message-ID: <20200104002152.GA32487@bogus> References: <20191224173942.18160-1-repk@triplefau.lt> <20191224173942.18160-5-repk@triplefau.lt> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191224173942.18160-5-repk@triplefau.lt> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Dec 24, 2019 at 06:39:41PM +0100, Remi Pommarel wrote: > Now that a new PHYs has been introduced for AXG SoC family, update > dt bindings documentation. This breaks compatibility. If that's okay, say so and why it is. If only someone had said putting the phy here in the first place was wrong: https://lore.kernel.org/linux-amlogic/20180829004122.GA25928@bogus/ > > Signed-off-by: Remi Pommarel > --- > .../bindings/pci/amlogic,meson-pcie.txt | 22 ++++++++----------- > 1 file changed, 9 insertions(+), 13 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > index 84fdc422792e..b6acbe694ffb 100644 > --- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > @@ -18,7 +18,6 @@ Required properties: > - reg-names: Must be > - "elbi" External local bus interface registers > - "cfg" Meson specific registers > - - "phy" Meson PCIE PHY registers for AXG SoC Family > - "config" PCIe configuration space > - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. > - clocks: Must contain an entry for each entry in clock-names. > @@ -26,13 +25,13 @@ Required properties: > - "pclk" PCIe GEN 100M PLL clock > - "port" PCIe_x(A or B) RC clock gate > - "general" PCIe Phy clock > - - "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family > - resets: phandle to the reset lines. > -- reset-names: must contain "phy" "port" and "apb" > - - "phy" Share PHY reset for AXG SoC Family > +- reset-names: must contain "port" and "apb" > - "port" Port A or B reset > - "apb" Share APB reset > -- phys: should contain a phandle to the shared phy for G12A SoC Family > +- phys: should contain a phandle to the PCIE phy > +- phy-names: must contain "pcie" > + > - device_type: > should be "pci". As specified in designware-pcie.txt > > @@ -43,9 +42,8 @@ Example configuration: > compatible = "amlogic,axg-pcie", "snps,dw-pcie"; > reg = <0x0 0xf9800000 0x0 0x400000 > 0x0 0xff646000 0x0 0x2000 > - 0x0 0xff644000 0x0 0x2000 > 0x0 0xf9f00000 0x0 0x100000>; > - reg-names = "elbi", "cfg", "phy", "config"; > + reg-names = "elbi", "cfg", "config"; > reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; > interrupts = ; > #interrupt-cells = <1>; > @@ -58,17 +56,15 @@ Example configuration: > ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; > > clocks = <&clkc CLKID_USB > - &clkc CLKID_MIPI_ENABLE > &clkc CLKID_PCIE_A > &clkc CLKID_PCIE_CML_EN0>; > clock-names = "general", > - "mipi", > "pclk", > "port"; > - resets = <&reset RESET_PCIE_PHY>, > - <&reset RESET_PCIE_A>, > + resets = <&reset RESET_PCIE_A>, > <&reset RESET_PCIE_APB>; > - reset-names = "phy", > - "port", > + reset-names = "port", > "apb"; > + phys = <&pcie_phy>; > + phy-names = "pcie"; > }; > -- > 2.24.0 >