From: Remi Pommarel <repk@triplefau.lt>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Yue Wang <yue.wang@Amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Rob Herring <robh+dt@kernel.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
Remi Pommarel <repk@triplefau.lt>
Subject: [PATCH v6 3/7] dt-bindings: PCI: meson: Update PCIE bindings documentation
Date: Fri, 24 Jan 2020 00:29:39 +0100 [thread overview]
Message-ID: <20200123232943.10229-4-repk@triplefau.lt> (raw)
In-Reply-To: <20200123232943.10229-1-repk@triplefau.lt>
Now that a new PHYs has been introduced for AXG SoC family, update
dt bindings documentation.
Please note that this breaks backward compatibility but as not a single
devicetree uses that yet that seems ok.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
---
.../bindings/pci/amlogic,meson-pcie.txt | 22 ++++++++-----------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
index 84fdc422792e..b6acbe694ffb 100644
--- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -18,7 +18,6 @@ Required properties:
- reg-names: Must be
- "elbi" External local bus interface registers
- "cfg" Meson specific registers
- - "phy" Meson PCIE PHY registers for AXG SoC Family
- "config" PCIe configuration space
- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
- clocks: Must contain an entry for each entry in clock-names.
@@ -26,13 +25,13 @@ Required properties:
- "pclk" PCIe GEN 100M PLL clock
- "port" PCIe_x(A or B) RC clock gate
- "general" PCIe Phy clock
- - "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family
- resets: phandle to the reset lines.
-- reset-names: must contain "phy" "port" and "apb"
- - "phy" Share PHY reset for AXG SoC Family
+- reset-names: must contain "port" and "apb"
- "port" Port A or B reset
- "apb" Share APB reset
-- phys: should contain a phandle to the shared phy for G12A SoC Family
+- phys: should contain a phandle to the PCIE phy
+- phy-names: must contain "pcie"
+
- device_type:
should be "pci". As specified in designware-pcie.txt
@@ -43,9 +42,8 @@ Example configuration:
compatible = "amlogic,axg-pcie", "snps,dw-pcie";
reg = <0x0 0xf9800000 0x0 0x400000
0x0 0xff646000 0x0 0x2000
- 0x0 0xff644000 0x0 0x2000
0x0 0xf9f00000 0x0 0x100000>;
- reg-names = "elbi", "cfg", "phy", "config";
+ reg-names = "elbi", "cfg", "config";
reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
#interrupt-cells = <1>;
@@ -58,17 +56,15 @@ Example configuration:
ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
clocks = <&clkc CLKID_USB
- &clkc CLKID_MIPI_ENABLE
&clkc CLKID_PCIE_A
&clkc CLKID_PCIE_CML_EN0>;
clock-names = "general",
- "mipi",
"pclk",
"port";
- resets = <&reset RESET_PCIE_PHY>,
- <&reset RESET_PCIE_A>,
+ resets = <&reset RESET_PCIE_A>,
<&reset RESET_PCIE_APB>;
- reset-names = "phy",
- "port",
+ reset-names = "port",
"apb";
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
};
--
2.24.1
next prev parent reply other threads:[~2020-01-23 23:22 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-23 23:29 [PATCH v6 0/7] PCI: amlogic: Make PCIe working reliably on AXG platforms Remi Pommarel
2020-01-23 23:29 ` [PATCH v6 1/7] dt-bindings: Add AXG PCIE PHY bindings Remi Pommarel
2020-01-24 8:27 ` Remi Pommarel
2020-01-23 23:29 ` [PATCH v6 2/7] dt-bindings: Add AXG shared MIPI/PCIE analog " Remi Pommarel
2020-01-24 8:28 ` Remi Pommarel
2020-01-23 23:29 ` Remi Pommarel [this message]
2020-01-24 8:30 ` [PATCH v6 3/7] dt-bindings: PCI: meson: Update PCIE bindings documentation Remi Pommarel
2020-01-23 23:29 ` [PATCH v6 4/7] arm64: dts: meson-axg: Add PCIE PHY nodes Remi Pommarel
2020-01-24 8:34 ` Remi Pommarel
2020-01-23 23:29 ` [PATCH v6 5/7] phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver Remi Pommarel
2020-01-24 8:32 ` Remi Pommarel
2020-03-03 17:19 ` Lorenzo Pieralisi
2020-03-04 9:08 ` Neil Armstrong
2020-03-04 10:44 ` Lorenzo Pieralisi
2020-01-23 23:29 ` [PATCH v6 6/7] phy: amlogic: Add Amlogic AXG PCIE " Remi Pommarel
2020-03-04 10:47 ` Neil Armstrong
2020-03-04 11:01 ` Kishon Vijay Abraham I
2020-03-04 13:08 ` Remi Pommarel
2020-03-05 4:56 ` Kishon Vijay Abraham I
2020-03-05 7:00 ` Neil Armstrong
2020-01-23 23:29 ` [PATCH v6 7/7] PCI: amlogic: Use AXG PCIE Remi Pommarel
2020-01-24 8:35 ` Remi Pommarel
2020-01-24 8:02 ` [PATCH v6 0/7] PCI: amlogic: Make PCIe working reliably on AXG platforms Neil Armstrong
2020-01-24 8:37 ` Remi Pommarel
2020-02-24 14:15 ` Lorenzo Pieralisi
2020-02-29 16:07 ` Kevin Hilman
2020-02-29 17:10 ` Remi Pommarel
2020-03-03 15:03 ` Lorenzo Pieralisi
2020-03-04 12:28 ` Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200123232943.10229-4-repk@triplefau.lt \
--to=repk@triplefau.lt \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=jbrunet@baylibre.com \
--cc=khilman@baylibre.com \
--cc=kishon@ti.com \
--cc=linux-amlogic@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=martin.blumenstingl@googlemail.com \
--cc=narmstrong@baylibre.com \
--cc=robh+dt@kernel.org \
--cc=yue.wang@Amlogic.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).