* [PATCH v2 0/2] dt-bindings: Convert Cadence PCIe RC/EP to DT Schema
@ 2020-02-17 11:15 Kishon Vijay Abraham I
2020-02-17 11:15 ` [PATCH v2 1/2] dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe Kishon Vijay Abraham I
2020-02-17 11:15 ` [PATCH v2 2/2] dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema Kishon Vijay Abraham I
0 siblings, 2 replies; 8+ messages in thread
From: Kishon Vijay Abraham I @ 2020-02-17 11:15 UTC (permalink / raw)
To: Rob Herring, Tom Joseph, Lorenzo Pieralisi, Andrew Murray
Cc: Mark Rutland, linux-pci, devicetree, linux-kernel,
Kishon Vijay Abraham I
Cadence PCIe IP is used by multiple SoC vendors (e.g. TI). Cadence
themselves have a validation platform for validating the PCIe IP which
is already in the upstream kernel. Right now the binding only exists for
Cadence platform and this will result in adding redundant binding schema
for any platform using Cadence PCIe core.
This series:
1) Create cdns-pcie.yaml which includes properties that are applicable
to both host mode and endpoint mode of Cadence PCIe core.
2) Create cdns-pcie-host.yaml to include properties that are specific to
host mode of Cadence PCIe core. cdns-pcie-host.yaml will include
cdns-pcie.yaml.
3) Create cdns-pcie-ep.yaml to include properties that are specific to
endpoint mode of Cadence PCIe core. cdns-pcie-ep.yaml will include
cdns-pcie.yaml.
4) Remove cdns,cdns-pcie-ep.txt and cdns,cdns-pcie-host.txt which had
the binding for Cadence "platform" and add cdns,cdns-pcie-host.yaml
and cdns,cdns-pcie-ep.yaml schema for Cadence Platform. The schema
for Cadence platform then includes schema for Cadence PCIe core.
Changes from v1:
*) Fix maximum values of num-lanes and cdns,no-bar-match-nbits
*) Fix example DT node for PCIe Endpoint.
Ref: Patches to convert Cadence driver to library
https://lkml.org/lkml/2019/11/11/317
Some of this was initially part of [1], but to accelerate it getting
into upstream, sending this as a separate series.
[1] -> [1] -> http://lore.kernel.org/r/20200106102058.19183-1-kishon@ti.com
Kishon Vijay Abraham I (2):
dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe
dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT
schema
.../bindings/pci/cdns,cdns-pcie-ep.txt | 27 -------
.../bindings/pci/cdns,cdns-pcie-ep.yaml | 48 ++++++++++++
.../bindings/pci/cdns,cdns-pcie-host.txt | 66 ----------------
.../bindings/pci/cdns,cdns-pcie-host.yaml | 76 +++++++++++++++++++
.../devicetree/bindings/pci/cdns-pcie-ep.yaml | 22 ++++++
.../bindings/pci/cdns-pcie-host.yaml | 27 +++++++
.../devicetree/bindings/pci/cdns-pcie.yaml | 45 +++++++++++
MAINTAINERS | 2 +-
8 files changed, 219 insertions(+), 94 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie.yaml
--
2.17.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2 1/2] dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe 2020-02-17 11:15 [PATCH v2 0/2] dt-bindings: Convert Cadence PCIe RC/EP to DT Schema Kishon Vijay Abraham I @ 2020-02-17 11:15 ` Kishon Vijay Abraham I 2020-02-19 20:27 ` Rob Herring 2020-02-17 11:15 ` [PATCH v2 2/2] dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema Kishon Vijay Abraham I 1 sibling, 1 reply; 8+ messages in thread From: Kishon Vijay Abraham I @ 2020-02-17 11:15 UTC (permalink / raw) To: Rob Herring, Tom Joseph, Lorenzo Pieralisi, Andrew Murray Cc: Mark Rutland, linux-pci, devicetree, linux-kernel, Kishon Vijay Abraham I Add PCIe Host (RC) and Endpoint (EP) device tree schema for Cadence PCIe core library. Platforms using Cadence PCIe core can include the schemas added here in the platform specific schemas. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- .../devicetree/bindings/pci/cdns-pcie-ep.yaml | 22 +++++++++ .../bindings/pci/cdns-pcie-host.yaml | 27 +++++++++++ .../devicetree/bindings/pci/cdns-pcie.yaml | 45 +++++++++++++++++++ 3 files changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml new file mode 100644 index 000000000000..b22d54605009 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence PCIe Endpoint + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: "cdns-pcie.yaml#" + +properties: + max-functions: + description: Maximum number of functions that can be configured + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + minimum: 1 + default: 1 + maximum: 256 diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml new file mode 100644 index 000000000000..ab6e43b636ec --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence PCIe Host + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: "/schemas/pci/pci-bus.yaml#" + - $ref: "cdns-pcie.yaml#" + +properties: + cdns,no-bar-match-nbits: + description: + Set into the no BAR match register to configure the number of least + significant bits kept during inbound (PCIe -> AXI) address translations + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 64 + default: 32 + + msi-parent: true diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml new file mode 100644 index 000000000000..fd690b062de1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence PCIe Core + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +properties: + max-link-speed: + description: maximum link speed + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 4 + + num-lanes: + description: maximum number of lanes + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 16 + + cdns,max-outbound-regions: + description: maximum number of outbound regions + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 32 + + phys: + description: + One per lane if more than one in the list. If only one PHY listed it must + manage all lanes. + minItems: 1 + maxItems: 16 + + phy-names: + items: + - const: pcie-phy + # FIXME: names when more than 1 -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe 2020-02-17 11:15 ` [PATCH v2 1/2] dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe Kishon Vijay Abraham I @ 2020-02-19 20:27 ` Rob Herring 0 siblings, 0 replies; 8+ messages in thread From: Rob Herring @ 2020-02-19 20:27 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Tom Joseph, Lorenzo Pieralisi, Andrew Murray, Mark Rutland, linux-pci, devicetree, linux-kernel On Mon, Feb 17, 2020 at 04:45:18PM +0530, Kishon Vijay Abraham I wrote: > Add PCIe Host (RC) and Endpoint (EP) device tree schema for Cadence > PCIe core library. Platforms using Cadence PCIe core can include the > schemas added here in the platform specific schemas. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > .../devicetree/bindings/pci/cdns-pcie-ep.yaml | 22 +++++++++ > .../bindings/pci/cdns-pcie-host.yaml | 27 +++++++++++ > .../devicetree/bindings/pci/cdns-pcie.yaml | 45 +++++++++++++++++++ > 3 files changed, 94 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml > create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml > create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml > new file mode 100644 > index 000000000000..b22d54605009 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml > @@ -0,0 +1,22 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Cadence PCIe Endpoint > + > +maintainers: > + - Tom Joseph <tjoseph@cadence.com> > + > +allOf: > + - $ref: "cdns-pcie.yaml#" > + > +properties: > + max-functions: > + description: Maximum number of functions that can be configured > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint8 > + minimum: 1 > + default: 1 > + maximum: 256 Create a pcie-ep.yaml and put this there as every endpoint binding seems to use this and I'm sure there's more properties to come. Also, the max can only be 255. > diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml > new file mode 100644 > index 000000000000..ab6e43b636ec > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml > @@ -0,0 +1,27 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Cadence PCIe Host > + > +maintainers: > + - Tom Joseph <tjoseph@cadence.com> > + > +allOf: > + - $ref: "/schemas/pci/pci-bus.yaml#" > + - $ref: "cdns-pcie.yaml#" > + > +properties: > + cdns,no-bar-match-nbits: > + description: > + Set into the no BAR match register to configure the number of least > + significant bits kept during inbound (PCIe -> AXI) address translations This should probably be deprecated IMO. This info should really be extracted from sizes in 'dma-ranges'. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 64 > + default: 32 > + > + msi-parent: true > diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml > new file mode 100644 > index 000000000000..fd690b062de1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml > @@ -0,0 +1,45 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Cadence PCIe Core > + > +maintainers: > + - Tom Joseph <tjoseph@cadence.com> > + > +properties: > + max-link-speed: > + description: maximum link speed > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 1 > + maximum: 4 Standard property in pci-bus.yaml, no need to define it again. > + > + num-lanes: > + description: maximum number of lanes > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 1 > + maximum: 16 This should be added to pci-bus.yaml. Assume here it is. > + > + cdns,max-outbound-regions: > + description: maximum number of outbound regions > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 1 > + maximum: 32 > + default: 32 This too should be deprecated IMO. It is nothing more than error checking number of 'ranges' entries. But deprecating should be a follow-up. > + > + phys: > + description: > + One per lane if more than one in the list. If only one PHY listed it must > + manage all lanes. > + minItems: 1 > + maxItems: 16 > + > + phy-names: > + items: > + - const: pcie-phy > + # FIXME: names when more than 1 > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/2] dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema 2020-02-17 11:15 [PATCH v2 0/2] dt-bindings: Convert Cadence PCIe RC/EP to DT Schema Kishon Vijay Abraham I 2020-02-17 11:15 ` [PATCH v2 1/2] dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe Kishon Vijay Abraham I @ 2020-02-17 11:15 ` Kishon Vijay Abraham I 2020-02-19 20:32 ` Rob Herring 1 sibling, 1 reply; 8+ messages in thread From: Kishon Vijay Abraham I @ 2020-02-17 11:15 UTC (permalink / raw) To: Rob Herring, Tom Joseph, Lorenzo Pieralisi, Andrew Murray Cc: Mark Rutland, linux-pci, devicetree, linux-kernel, Kishon Vijay Abraham I Include Cadence core DT schema and define the Cadence platform DT schema for both Host and Endpoint mode. Note: The Cadence core DT schema could be included for other platforms using Cadence PCIe core. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- .../bindings/pci/cdns,cdns-pcie-ep.txt | 27 ------- .../bindings/pci/cdns,cdns-pcie-ep.yaml | 48 ++++++++++++ .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ---------------- .../bindings/pci/cdns,cdns-pcie-host.yaml | 76 +++++++++++++++++++ MAINTAINERS | 2 +- 5 files changed, 125 insertions(+), 94 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt deleted file mode 100644 index 4a0475e2ba7e..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Cadence PCIe endpoint controller - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used. -- reg: Should contain the controller register base address and AXI interface - region base address respectively. -- reg-names: Must be "reg" and "mem" respectively. -- cdns,max-outbound-regions: Set to maximum number of outbound regions - -Optional properties: -- max-functions: Maximum number of functions that can be configured (default 1). -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fc000000 { - compatible = "cdns,cdns-pcie-ep"; - reg = <0x0 0xfc000000 0x0 0x01000000>, - <0x0 0x80000000 0x0 0x40000000>; - reg-names = "reg", "mem"; - cdns,max-outbound-regions = <16>; - max-functions = /bits/ 8 <8>; - phys = <&ep_phy0 &ep_phy1>; - phy-names = "pcie-lane0","pcie-lane1"; -}; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml new file mode 100644 index 000000000000..be7009dd190c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence PCIe EP Controller + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: "cdns-pcie-ep.yaml#" + +properties: + compatible: + const: cdns,cdns-pcie-ep + + reg: + maxItems: 2 + + reg-names: + items: + - const: reg + - const: mem + +required: + - reg + - reg-names + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie-ep@fc000000 { + compatible = "cdns,cdns-pcie-ep"; + reg = <0x0 0xfc000000 0x0 0x01000000>, + <0x0 0x80000000 0x0 0x40000000>; + reg-names = "reg", "mem"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <8>; + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt deleted file mode 100644 index 91de69c713a9..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt +++ /dev/null @@ -1,66 +0,0 @@ -* Cadence PCIe host controller - -This PCIe controller inherits the base properties defined in -host-generic-pci.txt. - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used. -- reg: Should contain the controller register base address, PCIe configuration - window base address, and AXI interface region base address respectively. -- reg-names: Must be "reg", "cfg" and "mem" respectively. -- #address-cells: Set to <3> -- #size-cells: Set to <2> -- device_type: Set to "pci" -- ranges: Ranges for the PCI memory and I/O regions -- #interrupt-cells: Set to <1> -- interrupt-map-mask and interrupt-map: Standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers. - -Optional properties: -- cdns,max-outbound-regions: Set to maximum number of outbound regions - (default 32) -- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the - number of least significant bits kept during inbound (PCIe -> AXI) address - translations (default 32) -- vendor-id: The PCI vendor ID (16 bits, default is design dependent) -- device-id: The PCI device ID (16 bits, default is design dependent) -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fb000000 { - compatible = "cdns,cdns-pcie-host"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - linux,pci-domain = <0>; - cdns,max-outbound-regions = <16>; - cdns,no-bar-match-nbits = <32>; - vendor-id = /bits/ 16 <0x17cd>; - device-id = /bits/ 16 <0x0200>; - - reg = <0x0 0xfb000000 0x0 0x01000000>, - <0x0 0x41000000 0x0 0x00001000>, - <0x0 0x40000000 0x0 0x04000000>; - reg-names = "reg", "cfg", "mem"; - - ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, - <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; - - #interrupt-cells = <0x1>; - - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; - - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - - msi-parent = <&its_pci>; - - phys = <&pcie_phy0>; - phy-names = "pcie-phy"; -}; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml new file mode 100644 index 000000000000..2f605297f862 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence PCIe host controller + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: "cdns-pcie-host.yaml#" + +properties: + compatible: + const: cdns,cdns-pcie-host + + reg: + maxItems: 3 + + reg-names: + items: + - const: reg + - const: cfg + - const: mem + + msi-parent: true + +required: + - reg + - reg-names + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@fb000000 { + compatible = "cdns,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <32>; + vendor-id = /bits/ 16 <0x17cd>; + device-id = /bits/ 16 <0x0200>; + + reg = <0x0 0xfb000000 0x0 0x01000000>, + <0x0 0x41000000 0x0 0x00001000>, + <0x0 0x40000000 0x0 0x04000000>; + reg-names = "reg", "cfg", "mem"; + + ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, + <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; + + #interrupt-cells = <0x1>; + + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; + + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + + msi-parent = <&its_pci>; + + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 38fe2f3f7b6f..e0402e001edd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12739,7 +12739,7 @@ PCI DRIVER FOR CADENCE PCIE IP M: Tom Joseph <tjoseph@cadence.com> L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/cdns,*.txt +F: Documentation/devicetree/bindings/pci/cdns,* F: drivers/pci/controller/pcie-cadence* PCI DRIVER FOR FREESCALE LAYERSCAPE -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema 2020-02-17 11:15 ` [PATCH v2 2/2] dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema Kishon Vijay Abraham I @ 2020-02-19 20:32 ` Rob Herring 2020-02-24 10:18 ` Kishon Vijay Abraham I 0 siblings, 1 reply; 8+ messages in thread From: Rob Herring @ 2020-02-19 20:32 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Tom Joseph, Lorenzo Pieralisi, Andrew Murray, Mark Rutland, linux-pci, devicetree, linux-kernel On Mon, Feb 17, 2020 at 04:45:19PM +0530, Kishon Vijay Abraham I wrote: > Include Cadence core DT schema and define the Cadence platform DT schema > for both Host and Endpoint mode. Note: The Cadence core DT schema could > be included for other platforms using Cadence PCIe core. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > .../bindings/pci/cdns,cdns-pcie-ep.txt | 27 ------- > .../bindings/pci/cdns,cdns-pcie-ep.yaml | 48 ++++++++++++ > .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ---------------- > .../bindings/pci/cdns,cdns-pcie-host.yaml | 76 +++++++++++++++++++ > MAINTAINERS | 2 +- > 5 files changed, 125 insertions(+), 94 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt > create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml > delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt > create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > new file mode 100644 > index 000000000000..2f605297f862 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > @@ -0,0 +1,76 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cadence PCIe host controller > + > +maintainers: > + - Tom Joseph <tjoseph@cadence.com> > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + - $ref: "cdns-pcie-host.yaml#" > + > +properties: > + compatible: > + const: cdns,cdns-pcie-host > + > + reg: > + maxItems: 3 > + > + reg-names: > + items: > + - const: reg > + - const: cfg > + - const: mem > + > + msi-parent: true > + > +required: > + - reg > + - reg-names > + > +examples: > + - | > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie@fb000000 { > + compatible = "cdns,cdns-pcie-host"; > + device_type = "pci"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x0 0xff>; > + linux,pci-domain = <0>; > + cdns,max-outbound-regions = <16>; > + cdns,no-bar-match-nbits = <32>; > + vendor-id = /bits/ 16 <0x17cd>; > + device-id = /bits/ 16 <0x0200>; Please make these 32-bit as that is what the spec says. > + > + reg = <0x0 0xfb000000 0x0 0x01000000>, > + <0x0 0x41000000 0x0 0x00001000>, > + <0x0 0x40000000 0x0 0x04000000>; > + reg-names = "reg", "cfg", "mem"; > + > + ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, > + <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; > + > + #interrupt-cells = <0x1>; > + > + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>, > + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>, > + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>, > + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; > + > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + > + msi-parent = <&its_pci>; > + > + phys = <&pcie_phy0>; > + phy-names = "pcie-phy"; > + }; > + }; > +... > diff --git a/MAINTAINERS b/MAINTAINERS > index 38fe2f3f7b6f..e0402e001edd 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -12739,7 +12739,7 @@ PCI DRIVER FOR CADENCE PCIE IP > M: Tom Joseph <tjoseph@cadence.com> > L: linux-pci@vger.kernel.org > S: Maintained > -F: Documentation/devicetree/bindings/pci/cdns,*.txt > +F: Documentation/devicetree/bindings/pci/cdns,* > F: drivers/pci/controller/pcie-cadence* > > PCI DRIVER FOR FREESCALE LAYERSCAPE > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema 2020-02-19 20:32 ` Rob Herring @ 2020-02-24 10:18 ` Kishon Vijay Abraham I 2020-02-24 15:26 ` Rob Herring 0 siblings, 1 reply; 8+ messages in thread From: Kishon Vijay Abraham I @ 2020-02-24 10:18 UTC (permalink / raw) To: Rob Herring Cc: Tom Joseph, Lorenzo Pieralisi, Andrew Murray, Mark Rutland, linux-pci, devicetree, linux-kernel Hi Rob, On 20/02/20 2:02 am, Rob Herring wrote: > On Mon, Feb 17, 2020 at 04:45:19PM +0530, Kishon Vijay Abraham I wrote: >> Include Cadence core DT schema and define the Cadence platform DT schema >> for both Host and Endpoint mode. Note: The Cadence core DT schema could >> be included for other platforms using Cadence PCIe core. >> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >> --- >> .../bindings/pci/cdns,cdns-pcie-ep.txt | 27 ------- >> .../bindings/pci/cdns,cdns-pcie-ep.yaml | 48 ++++++++++++ >> .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ---------------- >> .../bindings/pci/cdns,cdns-pcie-host.yaml | 76 +++++++++++++++++++ >> MAINTAINERS | 2 +- >> 5 files changed, 125 insertions(+), 94 deletions(-) >> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt >> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml >> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt >> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > > >> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml >> new file mode 100644 >> index 000000000000..2f605297f862 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml >> @@ -0,0 +1,76 @@ >> +# SPDX-License-Identifier: GPL-2.0-only >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Cadence PCIe host controller >> + >> +maintainers: >> + - Tom Joseph <tjoseph@cadence.com> >> + >> +allOf: >> + - $ref: /schemas/pci/pci-bus.yaml# >> + - $ref: "cdns-pcie-host.yaml#" >> + >> +properties: >> + compatible: >> + const: cdns,cdns-pcie-host >> + >> + reg: >> + maxItems: 3 >> + >> + reg-names: >> + items: >> + - const: reg >> + - const: cfg >> + - const: mem >> + >> + msi-parent: true >> + >> +required: >> + - reg >> + - reg-names >> + >> +examples: >> + - | >> + bus { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + pcie@fb000000 { >> + compatible = "cdns,cdns-pcie-host"; >> + device_type = "pci"; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + bus-range = <0x0 0xff>; >> + linux,pci-domain = <0>; >> + cdns,max-outbound-regions = <16>; >> + cdns,no-bar-match-nbits = <32>; > >> + vendor-id = /bits/ 16 <0x17cd>; >> + device-id = /bits/ 16 <0x0200>; > > Please make these 32-bit as that is what the spec says. Can you clarify this is mentioned in which spec? PCI spec has both of these 16 bits and I checked the PCI binding doc but couldn't spot the size of these fields. [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf Thanks Kishon ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema 2020-02-24 10:18 ` Kishon Vijay Abraham I @ 2020-02-24 15:26 ` Rob Herring 2020-02-25 4:59 ` Kishon Vijay Abraham I 0 siblings, 1 reply; 8+ messages in thread From: Rob Herring @ 2020-02-24 15:26 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Tom Joseph, Lorenzo Pieralisi, Andrew Murray, Mark Rutland, PCI, devicetree, linux-kernel On Mon, Feb 24, 2020 at 4:14 AM Kishon Vijay Abraham I <kishon@ti.com> wrote: > > Hi Rob, > > On 20/02/20 2:02 am, Rob Herring wrote: > > On Mon, Feb 17, 2020 at 04:45:19PM +0530, Kishon Vijay Abraham I wrote: > >> Include Cadence core DT schema and define the Cadence platform DT schema > >> for both Host and Endpoint mode. Note: The Cadence core DT schema could > >> be included for other platforms using Cadence PCIe core. > >> > >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > >> --- > >> .../bindings/pci/cdns,cdns-pcie-ep.txt | 27 ------- > >> .../bindings/pci/cdns,cdns-pcie-ep.yaml | 48 ++++++++++++ > >> .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ---------------- > >> .../bindings/pci/cdns,cdns-pcie-host.yaml | 76 +++++++++++++++++++ > >> MAINTAINERS | 2 +- > >> 5 files changed, 125 insertions(+), 94 deletions(-) > >> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt > >> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml > >> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt > >> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > > > > > >> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > >> new file mode 100644 > >> index 000000000000..2f605297f862 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > >> @@ -0,0 +1,76 @@ > >> +# SPDX-License-Identifier: GPL-2.0-only > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: Cadence PCIe host controller > >> + > >> +maintainers: > >> + - Tom Joseph <tjoseph@cadence.com> > >> + > >> +allOf: > >> + - $ref: /schemas/pci/pci-bus.yaml# > >> + - $ref: "cdns-pcie-host.yaml#" > >> + > >> +properties: > >> + compatible: > >> + const: cdns,cdns-pcie-host > >> + > >> + reg: > >> + maxItems: 3 > >> + > >> + reg-names: > >> + items: > >> + - const: reg > >> + - const: cfg > >> + - const: mem > >> + > >> + msi-parent: true > >> + > >> +required: > >> + - reg > >> + - reg-names > >> + > >> +examples: > >> + - | > >> + bus { > >> + #address-cells = <2>; > >> + #size-cells = <2>; > >> + > >> + pcie@fb000000 { > >> + compatible = "cdns,cdns-pcie-host"; > >> + device_type = "pci"; > >> + #address-cells = <3>; > >> + #size-cells = <2>; > >> + bus-range = <0x0 0xff>; > >> + linux,pci-domain = <0>; > >> + cdns,max-outbound-regions = <16>; > >> + cdns,no-bar-match-nbits = <32>; > > > >> + vendor-id = /bits/ 16 <0x17cd>; > >> + device-id = /bits/ 16 <0x0200>; > > > > Please make these 32-bit as that is what the spec says. > > Can you clarify this is mentioned in which spec? PCI spec has both of > these 16 bits and I checked the PCI binding doc but couldn't spot the > size of these fields. > > [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf Section 4.1.2.1. The key point is the type is 'encode-int' which means 32-bit. Keep in mind, that 16-bits was not a defined type when this spec was written. We added that for FDT. Also, look at other instances of reading 'vendor-id' in the kernel. Rob ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema 2020-02-24 15:26 ` Rob Herring @ 2020-02-25 4:59 ` Kishon Vijay Abraham I 0 siblings, 0 replies; 8+ messages in thread From: Kishon Vijay Abraham I @ 2020-02-25 4:59 UTC (permalink / raw) To: Rob Herring Cc: Tom Joseph, Lorenzo Pieralisi, Andrew Murray, Mark Rutland, PCI, devicetree, linux-kernel Rob, On 24/02/20 8:56 pm, Rob Herring wrote: > On Mon, Feb 24, 2020 at 4:14 AM Kishon Vijay Abraham I <kishon@ti.com> wrote: >> >> Hi Rob, >> >> On 20/02/20 2:02 am, Rob Herring wrote: >>> On Mon, Feb 17, 2020 at 04:45:19PM +0530, Kishon Vijay Abraham I wrote: >>>> Include Cadence core DT schema and define the Cadence platform DT schema >>>> for both Host and Endpoint mode. Note: The Cadence core DT schema could >>>> be included for other platforms using Cadence PCIe core. >>>> >>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >>>> --- >>>> .../bindings/pci/cdns,cdns-pcie-ep.txt | 27 ------- >>>> .../bindings/pci/cdns,cdns-pcie-ep.yaml | 48 ++++++++++++ >>>> .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ---------------- >>>> .../bindings/pci/cdns,cdns-pcie-host.yaml | 76 +++++++++++++++++++ >>>> MAINTAINERS | 2 +- >>>> 5 files changed, 125 insertions(+), 94 deletions(-) >>>> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt >>>> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml >>>> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt >>>> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml >>> >>> >>>> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml >>>> new file mode 100644 >>>> index 000000000000..2f605297f862 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml >>>> @@ -0,0 +1,76 @@ >>>> +# SPDX-License-Identifier: GPL-2.0-only >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Cadence PCIe host controller >>>> + >>>> +maintainers: >>>> + - Tom Joseph <tjoseph@cadence.com> >>>> + >>>> +allOf: >>>> + - $ref: /schemas/pci/pci-bus.yaml# >>>> + - $ref: "cdns-pcie-host.yaml#" >>>> + >>>> +properties: >>>> + compatible: >>>> + const: cdns,cdns-pcie-host >>>> + >>>> + reg: >>>> + maxItems: 3 >>>> + >>>> + reg-names: >>>> + items: >>>> + - const: reg >>>> + - const: cfg >>>> + - const: mem >>>> + >>>> + msi-parent: true >>>> + >>>> +required: >>>> + - reg >>>> + - reg-names >>>> + >>>> +examples: >>>> + - | >>>> + bus { >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + >>>> + pcie@fb000000 { >>>> + compatible = "cdns,cdns-pcie-host"; >>>> + device_type = "pci"; >>>> + #address-cells = <3>; >>>> + #size-cells = <2>; >>>> + bus-range = <0x0 0xff>; >>>> + linux,pci-domain = <0>; >>>> + cdns,max-outbound-regions = <16>; >>>> + cdns,no-bar-match-nbits = <32>; >>> >>>> + vendor-id = /bits/ 16 <0x17cd>; >>>> + device-id = /bits/ 16 <0x0200>; >>> >>> Please make these 32-bit as that is what the spec says. >> >> Can you clarify this is mentioned in which spec? PCI spec has both of >> these 16 bits and I checked the PCI binding doc but couldn't spot the >> size of these fields. >> >> [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf > > Section 4.1.2.1. The key point is the type is 'encode-int' which means > 32-bit. Keep in mind, that 16-bits was not a defined type when this > spec was written. We added that for FDT. > > Also, look at other instances of reading 'vendor-id' in the kernel. Thanks for clarifying. Regards Kishon ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-02-25 4:56 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-02-17 11:15 [PATCH v2 0/2] dt-bindings: Convert Cadence PCIe RC/EP to DT Schema Kishon Vijay Abraham I 2020-02-17 11:15 ` [PATCH v2 1/2] dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe Kishon Vijay Abraham I 2020-02-19 20:27 ` Rob Herring 2020-02-17 11:15 ` [PATCH v2 2/2] dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema Kishon Vijay Abraham I 2020-02-19 20:32 ` Rob Herring 2020-02-24 10:18 ` Kishon Vijay Abraham I 2020-02-24 15:26 ` Rob Herring 2020-02-25 4:59 ` Kishon Vijay Abraham I
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