From: Matthias Kaehlcke <mka@chromium.org>
To: Akash Asthana <akashast@codeaurora.org>
Cc: gregkh@linuxfoundation.org, agross@kernel.org,
bjorn.andersson@linaro.org, wsa@the-dreams.de,
broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org,
linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, swboyd@chromium.org,
mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org,
linux-serial@vger.kernel.org, dianders@chromium.org,
evgreen@chromium.org
Subject: Re: [PATCH V2 4/8] tty: serial: qcom_geni_serial: Add interconnect support
Date: Fri, 13 Mar 2020 14:28:33 -0700 [thread overview]
Message-ID: <20200313212833.GK144492@google.com> (raw)
In-Reply-To: <1584105134-13583-5-git-send-email-akashast@codeaurora.org>
Hi Akash,
On Fri, Mar 13, 2020 at 06:42:10PM +0530, Akash Asthana wrote:
> Get the interconnect paths for Uart based Serial Engine device
> and vote according to the baud rate requirement of the driver.
>
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
> Changes in V2:
> - As per Bjorn's comment, removed se == NULL check from geni_serial_icc_get
> - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure
> - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
> path handle
> - As per Matthias comment, added error handling for icc_set_bw call
>
> drivers/tty/serial/qcom_geni_serial.c | 69 +++++++++++++++++++++++++++++++++--
> 1 file changed, 65 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
> index 272bae0..c8ad7e9 100644
> --- a/drivers/tty/serial/qcom_geni_serial.c
> +++ b/drivers/tty/serial/qcom_geni_serial.c
> @@ -184,6 +184,19 @@ static struct qcom_geni_serial_port qcom_geni_console_port = {
> },
> };
>
> +static int geni_serial_icc_get(struct geni_se *se)
> +{
> + se->icc_path_geni_to_core = devm_of_icc_get(se->dev, "qup-core");
> + if (IS_ERR(se->icc_path_geni_to_core))
> + return PTR_ERR(se->icc_path_geni_to_core);
> +
> + se->icc_path_cpu_to_geni = devm_of_icc_get(se->dev, "qup-config");
> + if (IS_ERR(se->icc_path_cpu_to_geni))
> + return PTR_ERR(se->icc_path_cpu_to_geni);
> +
> + return 0;
> +}
> +
> static int qcom_geni_serial_request_port(struct uart_port *uport)
> {
> struct platform_device *pdev = to_platform_device(uport->dev);
> @@ -962,6 +975,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
> struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
> unsigned long clk_rate;
> u32 ver, sampling_rate;
> + int ret;
>
> qcom_geni_serial_stop_rx(uport);
> /* baud rate */
> @@ -983,6 +997,18 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
> ser_clk_cfg = SER_CLK_EN;
> ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
>
> + /*
> + * Put BW vote only on CPU path as driver supports FIFO mode only.
> + * Assume peak_bw as twice of avg_bw.
> + */
> + port->se.avg_bw_cpu = Bps_to_icc(baud);
> + port->se.peak_bw_cpu = Bps_to_icc(2 * baud);
> + ret = icc_set_bw(port->se.icc_path_cpu_to_geni, port->se.avg_bw_cpu,
> + port->se.peak_bw_cpu);
> + if (ret)
> + dev_err(uport->dev, "%s: ICC BW voting failed for cpu\n",
> + __func__);
Should this return an error? The port might not operate properly if the ICC
bandwidth couldn't be configured
> +
> /* parity */
> tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
> tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
> @@ -1208,16 +1234,40 @@ static void qcom_geni_serial_pm(struct uart_port *uport,
> unsigned int new_state, unsigned int old_state)
> {
> struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
> -
> + int ret;
> /* If we've never been called, treat it as off */
> if (old_state == UART_PM_STATE_UNDEFINED)
> old_state = UART_PM_STATE_OFF;
>
> - if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
> + if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
> + /* Put BW vote for core clocks and CPU */
> + ret = icc_set_bw(port->se.icc_path_geni_to_core,
> + port->se.avg_bw_core, port->se.peak_bw_core);
> + if (ret)
> + dev_err(uport->dev, "%s: ICC BW voting failed for core\n",
> + __func__);
> +
> + ret = icc_set_bw(port->se.icc_path_cpu_to_geni,
> + port->se.avg_bw_cpu, port->se.peak_bw_cpu);
> + if (ret)
> + dev_err(uport->dev, "%s: ICC BW voting failed for cpu\n",
> + __func__);
> +
> geni_se_resources_on(&port->se);
> - else if (new_state == UART_PM_STATE_OFF &&
> - old_state == UART_PM_STATE_ON)
> + } else if (new_state == UART_PM_STATE_OFF &&
> + old_state == UART_PM_STATE_ON) {
> geni_se_resources_off(&port->se);
> + /* Remove BW vote from core clocks and CPU */
> + ret = icc_set_bw(port->se.icc_path_geni_to_core, 0, 0);
> + if (ret)
> + dev_err(uport->dev, "%s: ICC BW remove failed for core\n",
> + __func__);
> +
> + ret = icc_set_bw(port->se.icc_path_cpu_to_geni, 0, 0);
> + if (ret)
> + dev_err(uport->dev, "%s: ICC BW remove failed for cpu\n",
> + __func__);
> + }
> }
>
> static const struct uart_ops qcom_geni_console_pops = {
> @@ -1308,6 +1358,17 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
> port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
> port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
>
> + ret = geni_serial_icc_get(&port->se);
> + if (ret)
> + return ret;
> + /* Set the bus quota to a reasonable value */
> + port->se.avg_bw_core = console ? Bps_to_icc(1000) :
> + Bps_to_icc(CORE_2X_50_MHZ);
Why different settings for console vs. non-console?
> + port->se.peak_bw_core = console ? Bps_to_icc(1000) :
> + Bps_to_icc(CORE_2X_100_MHZ);
> + port->se.avg_bw_cpu = Bps_to_icc(1000);
> + port->se.peak_bw_cpu = Bps_to_icc(1000);
'Bps_to_icc(1000)' is a recurring theme in this series, could it be worth
to have a constant for that? Could be GENI_DEFAULT_BW or similar.
next prev parent reply other threads:[~2020-03-13 21:28 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-13 13:12 [PATCH V2 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
2020-03-13 13:12 ` [PATCH V2 1/8] interconnect: Add devm_of_icc_get() as exported API for users Akash Asthana
2020-03-13 16:26 ` Matthias Kaehlcke
2020-03-27 23:02 ` Bjorn Andersson
2020-03-13 13:12 ` [PATCH V2 2/8] soc: qcom: geni: Support for ICC voting Akash Asthana
2020-03-13 16:42 ` Matthias Kaehlcke
2020-03-17 9:58 ` Akash Asthana
2020-03-17 19:06 ` Evan Green
[not found] ` <74851dda-296d-cdc5-2449-b9ec59bbc057@codeaurora.org>
2020-03-20 16:45 ` Evan Green
2020-03-27 5:33 ` Akash Asthana
2020-03-13 13:12 ` [PATCH V2 3/8] soc: qcom-geni-se: Add interconnect support to fix earlycon crash Akash Asthana
2020-03-13 20:44 ` Matthias Kaehlcke
2020-03-17 10:57 ` Akash Asthana
2020-03-17 18:29 ` Matthias Kaehlcke
2020-03-18 8:54 ` Akash Asthana
2020-03-19 19:43 ` Matthias Kaehlcke
2020-03-20 10:22 ` Akash Asthana
2020-03-20 16:30 ` Evan Green
2020-03-27 5:04 ` Akash Asthana
2020-03-27 23:23 ` Bjorn Andersson
2020-03-31 10:55 ` Akash Asthana
2020-03-17 19:08 ` Evan Green
2020-03-17 19:46 ` Doug Anderson
2020-03-18 10:57 ` Akash Asthana
2020-03-18 16:22 ` Evan Green
2020-03-13 13:12 ` [PATCH V2 4/8] tty: serial: qcom_geni_serial: Add interconnect support Akash Asthana
2020-03-13 21:28 ` Matthias Kaehlcke [this message]
2020-03-17 11:48 ` Akash Asthana
2020-03-17 19:08 ` Matthias Kaehlcke
2020-03-18 12:23 ` Akash Asthana
2020-03-19 20:42 ` Matthias Kaehlcke
2020-03-20 10:35 ` Akash Asthana
2020-03-13 13:12 ` [PATCH V2 5/8] i2c: i2c-qcom-geni: " Akash Asthana
2020-03-14 0:17 ` Matthias Kaehlcke
2020-03-17 11:51 ` Akash Asthana
2020-03-13 13:12 ` [PATCH V2 6/8] spi: spi-geni-qcom: " Akash Asthana
2020-03-13 13:16 ` Mark Brown
2020-03-17 9:35 ` Akash Asthana
2020-03-17 13:06 ` Mark Brown
2020-03-20 13:52 ` Akash Asthana
2020-03-14 0:41 ` Matthias Kaehlcke
2020-03-17 12:11 ` Akash Asthana
2020-03-13 13:12 ` [PATCH V2 7/8] spi: spi-qcom-qspi: " Akash Asthana
2020-03-14 0:58 ` Matthias Kaehlcke
2020-03-17 12:13 ` Akash Asthana
2020-03-17 19:08 ` Evan Green
2020-03-18 13:48 ` Akash Asthana
2020-03-18 16:30 ` Evan Green
2020-03-20 5:35 ` Akash Asthana
2020-03-13 13:12 ` [PATCH V2 8/8] arm64: dts: sc7180: Add interconnect for QUP and QSPI Akash Asthana
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