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From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Thomas Gleixner <tglx@linutronix.de>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	Serge Semin <fancer.lancer@gmail.com>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	Paul Burton <paulburton@kernel.org>,
	Ralf Baechle <ralf@linux-mips.org>,
	Alessandro Zummo <a.zummo@towertech.it>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Arnd Bergmann <arnd@arndb.de>, Rob Herring <robh+dt@kernel.org>,
	<linux-mips@vger.kernel.org>, <linux-rtc@vger.kernel.org>,
	<devicetree@vger.kernel.org>,
	afzal mohammed <afzal.mohd.ma@gmail.com>,
	Allison Randal <allison@lohutok.net>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH v5 4/8] clocksource: dw_apb_timer: Make CPU-affiliation being optional
Date: Thu, 21 May 2020 23:48:13 +0300
Message-ID: <20200521204818.25436-5-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20200521204818.25436-1-Sergey.Semin@baikalelectronics.ru>

Currently the DW APB Timer driver binds each clockevent timers to a
particular CPU. This isn't good for multiple reasons. First of all seeing
the device is placed on APB bus (which makes it accessible from any CPU
core), accessible over MMIO and having the DYNIRQ flag set we can be sure
that manually binding the timer to any CPU just isn't correct. By doing
so we just set an extra limitation on device usage. This also doesn't
reflect the device actual capability, since by setting the IRQ affinity
we can make it virtually local to any CPU. Secondly imagine if you had a
real CPU-local timer with the same rating and the same CPU-affinity.
In this case if DW APB timer was registered first, then due to the
clockevent framework tick-timer selection procedure we'll end up with the
real CPU-local timer being left unselected for clock-events tracking. But
on most of the platforms (MIPS/ARM/etc) such timers are normally embedded
into the CPU core and are accessible with much better performance then
devices placed on APB. For instance in MIPS architectures there is
r4k-timer, which is CPU-local, assigned with the same rating, and normally
its clockevent device is registered after the platform-specific one.

So in order to fix all of these issues let's make the DW APB Timer CPU
affinity being optional and deactivated by passing a negative CPU id,
which will effectively set the DW APB clockevent timer cpumask to
'cpu_possible_mask'.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: devicetree@vger.kernel.org

---

Changelog v5:
- Don't discard CPU affiliation functionality, but allow it being optional.
  If CPU id passed to the clockevent registration method is negative, then
  don't assign the timer events to any particular CPU.
- Discard the OF-based DW APB Timer CPU-affiliation setting change. It'll
  be moved to a dedicated patch.
---
 drivers/clocksource/dw_apb_timer.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c
index b207a77b0831..f5f24a95ee82 100644
--- a/drivers/clocksource/dw_apb_timer.c
+++ b/drivers/clocksource/dw_apb_timer.c
@@ -222,7 +222,8 @@ static int apbt_next_event(unsigned long delta,
 /**
  * dw_apb_clockevent_init() - use an APB timer as a clock_event_device
  *
- * @cpu:	The CPU the events will be targeted at.
+ * @cpu:	The CPU the events will be targeted at or -1 if CPU affiliation
+ *		isn't required.
  * @name:	The name used for the timer and the IRQ for it.
  * @rating:	The rating to give the timer.
  * @base:	I/O base for the timer registers.
@@ -257,7 +258,7 @@ dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
 	dw_ced->ced.max_delta_ticks = 0x7fffffff;
 	dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
 	dw_ced->ced.min_delta_ticks = 5000;
-	dw_ced->ced.cpumask = cpumask_of(cpu);
+	dw_ced->ced.cpumask = cpu < 0 ? cpu_possible_mask : cpumask_of(cpu);
 	dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC |
 				CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
 	dw_ced->ced.set_state_shutdown = apbt_shutdown;
-- 
2.25.1


  parent reply index

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-21 20:48 [PATCH v5 0/8] clocksource: Fix MIPS GIC and DW APB Timer for Baikal-T1 SoC support Serge Semin
2020-05-21 20:48 ` [PATCH v5 1/8] dt-bindings: rtc: Convert snps,dw-apb-timer to DT schema Serge Semin
2020-05-21 20:48 ` [PATCH v5 2/8] dt-bindings: timer: Move snps,dw-apb-timer DT schema from rtc Serge Semin
2020-05-21 20:48 ` [PATCH v5 3/8] dt-bindings: interrupt-controller: Convert mti,gic to DT schema Serge Semin
2020-05-21 20:48 ` Serge Semin [this message]
2020-06-01 13:11   ` [tip: timers/core] clocksource: dw_apb_timer: Make CPU-affiliation being optional tip-bot2 for Serge Semin
2020-05-21 20:48 ` [PATCH v5 5/8] clocksource: dw_apb_timer: Affiliate of-based timer with any CPU Serge Semin
2020-06-01 13:11   ` [tip: timers/core] " tip-bot2 for Serge Semin
2020-05-21 20:48 ` [PATCH v5 6/8] clocksource: dw_apb_timer_of: Fix missing clockevent timers Serge Semin
2020-06-01 13:11   ` [tip: timers/core] " tip-bot2 for Serge Semin
2020-05-21 20:48 ` [PATCH v5 7/8] clocksource: mips-gic-timer: Register as sched_clock Serge Semin
2020-06-01 13:11   ` [tip: timers/core] " tip-bot2 for Paul Burton
2020-05-21 20:48 ` [PATCH v5 8/8] clocksource: mips-gic-timer: Mark GIC timer as unstable if ref clock changes Serge Semin
2020-06-01 13:11   ` [tip: timers/core] " tip-bot2 for Serge Semin
2020-05-22 15:28 ` [PATCH v5 0/8] clocksource: Fix MIPS GIC and DW APB Timer for Baikal-T1 SoC support Daniel Lezcano
2020-05-22 15:41   ` Serge Semin
2020-05-22 15:44     ` Daniel Lezcano
2020-05-22 16:02       ` Serge Semin

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