[PATCH/RFC 0/5] ravb: Add support for explicit internal clock delay configuration

[PATCH/RFC 0/5] ravb: Add support for explicit internal clock delay configuration

[Geert Uytterhoeven]

	Hi all,

Some Renesas EtherAVB variants support internal clock delay
configuration, which can add larger delays than the delays that are
typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or
"[rt]xc-skew-ps" properties).

Historically, the EtherAVB driver configured these delays based on the
"rgmii-*id" PHY mode.  This caused issues with PHY drivers that
implement PHY internal delays properly[1].  Hence a backwards-compatible
workaround was added by masking the PHY mode[2].

This RFC patch series implements the next step of the plan outlined in
[3], and adds proper support for explicit configuration of the MAC
internal clock delays using new "renesas,[rt]xc-delay-ps" properties.
If none of these properties is present, the driver falls back to the old
handling.

The series consists of 4 parts:
  1. DT binding update documenting the new properties,
  2. A preparatory improvement,
  3. Driver update implementing support for the new properties,
  4. DT updates, one for R-Car Gen3 and RZ/G2 SoC families each.

Note that patches 4 and 5 depend on patch 3, and must not be applied
before that dependency has hit upstream.

Impacted, tested:
  - Salvator-X(S) with R-Car H3 ES1.0 and ES2.0, M3-W, and M3-N.

Not impacted, tested:
  - Ebisu with R-Car E3.

Impacted, not tested:
  - Salvator-X(S) with other SoC variants,
  - ULCB with R-Car H3/M3-W/M3-N variants,
  - V3MSK and Eagle with R-Car V3M,
  - Draak with R-Car V3H,
  - HiHope RZ/G2[MN] with RZ/G2M or RZ/G2N.

Thanks for your comments!

References:
  [1] Commit bcf3440c6dd78bfe ("net: phy: micrel: add phy-mode support
      for the KSZ9031 PHY")
  [2] Commit 9b23203c32ee02cd ("ravb: Mask PHY mode to avoid inserting
      delays twice").
      https://lore.kernel.org/r/20200529122540.31368-1-geert+renesas@glider.be/
  [3] https://lore.kernel.org/r/CAMuHMdU+MR-2tr3-pH55G0GqPG9HwH3XUd=8HZxprFDMGQeWUw@mail.gmail.com/

Geert Uytterhoeven (5):
  dt-bindings: net: renesas,ravb: Document internal clock delay
    properties
  ravb: Split delay handling in parsing and applying
  ravb: Add support for explicit internal clock delay configuration
  arm64: dts: renesas: rcar-gen3: Convert EtherAVB to explicit delay
    handling
  arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling

 .../devicetree/bindings/net/renesas,ravb.txt  | 29 ++++++-----
 .../boot/dts/renesas/hihope-rzg2-ex.dtsi      |  2 +-
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi     |  1 +
 arch/arm64/boot/dts/renesas/r8a77951.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a77960.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a77961.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a77965.dtsi     |  2 +
 .../arm64/boot/dts/renesas/r8a77970-eagle.dts |  3 +-
 .../arm64/boot/dts/renesas/r8a77970-v3msk.dts |  3 +-
 arch/arm64/boot/dts/renesas/r8a77970.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a77980.dtsi     |  2 +
 arch/arm64/boot/dts/renesas/r8a77990.dtsi     |  1 +
 arch/arm64/boot/dts/renesas/r8a77995.dtsi     |  1 +
 .../boot/dts/renesas/salvator-common.dtsi     |  2 +-
 arch/arm64/boot/dts/renesas/ulcb.dtsi         |  2 +-
 drivers/net/ethernet/renesas/ravb.h           |  5 +-
 drivers/net/ethernet/renesas/ravb_main.c      | 52 ++++++++++++++-----
 19 files changed, 86 insertions(+), 31 deletions(-)

-- 
2.17.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH/RFC 1/5] dt-bindings: net: renesas,ravb: Document internal clock delay properties

[Geert Uytterhoeven]

Some EtherAVB variants support internal clock delay configuration, which
can add larger delays than the delays that are typically supported by
the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
properties).

Add properties for configuring the internal MAC delays.
These properties are mandatory, even when specified as zero, to
distinguish between old and new DTBs.

Update the example accordingly.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 .../devicetree/bindings/net/renesas,ravb.txt  | 29 ++++++++++---------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
index 032b76f14f4fdb38..488ada78b6169b8e 100644
--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
+++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
@@ -64,6 +64,18 @@ Optional properties:
 			 AVB_LINK signal.
 - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
 				 active-low instead of normal active-high.
+- renesas,rxc-delay-ps: Internal RX clock delay.
+			This property is mandatory and valid only on R-Car Gen3
+			and RZ/G2 SoCs.
+			Valid values are 0 and 1800.
+			A non-zero value is allowed only if phy-mode = "rgmii".
+			Zero is not supported on R-Car D3.
+- renesas,txc-delay-ps: Internal TX clock delay.
+			This property is mandatory and valid only on R-Car H3,
+			M3-W, M3-W+, M3-N, V3M, and V3H, and RZ/G2M and RZ/G2N.
+			Valid values are 0 and 2000.
+			A non-zero value is allowed only if phy-mode = "rgmii".
+			Zero is not supported on R-Car V3H.
 
 Example:
 
@@ -105,8 +117,10 @@ Example:
 				  "ch24";
 		clocks = <&cpg CPG_MOD 812>;
 		power-domains = <&cpg>;
-		phy-mode = "rgmii-id";
+		phy-mode = "rgmii";
 		phy-handle = <&phy0>;
+		renesas,rxc-delay-ps = <0>;
+		renesas,txc-delay-ps = <2000>;
 
 		pinctrl-0 = <&ether_pins>;
 		pinctrl-names = "default";
@@ -115,18 +129,7 @@ Example:
 		#size-cells = <0>;
 
 		phy0: ethernet-phy@0 {
-			rxc-skew-ps = <900>;
-			rxdv-skew-ps = <0>;
-			rxd0-skew-ps = <0>;
-			rxd1-skew-ps = <0>;
-			rxd2-skew-ps = <0>;
-			rxd3-skew-ps = <0>;
-			txc-skew-ps = <900>;
-			txen-skew-ps = <0>;
-			txd0-skew-ps = <0>;
-			txd1-skew-ps = <0>;
-			txd2-skew-ps = <0>;
-			txd3-skew-ps = <0>;
+			rxc-skew-ps = <1500>;
 			reg = <0>;
 			interrupt-parent = <&gpio2>;
 			interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
-- 
2.17.1

[PATCH/RFC 2/5] ravb: Split delay handling in parsing and applying

[Geert Uytterhoeven]

Currently, full delay handling is done in both the probe and resume
paths.  Split it in two parts, so the resume path doesn't have to redo
the parsing part over and over again.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/net/ethernet/renesas/ravb.h      |  4 +++-
 drivers/net/ethernet/renesas/ravb_main.c | 21 ++++++++++++++++-----
 2 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index 9f88b5db4f89843a..e5ca12ce93c730a9 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -1036,7 +1036,9 @@ struct ravb_private {
 	unsigned no_avb_link:1;
 	unsigned avb_link_active_low:1;
 	unsigned wol_enabled:1;
-	int num_tx_desc;	/* TX descriptors per packet */
+	unsigned rxcidm:1;		/* RX Clock Internal Delay Mode */
+	unsigned txcidm:1;		/* TX Clock Internal Delay Mode */
+	int num_tx_desc;		/* TX descriptors per packet */
 };
 
 static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index a442bcf64b9cd875..f326234d1940f43e 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -1967,23 +1967,32 @@ static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = {
 };
 
 /* Set tx and rx clock internal delay modes */
-static void ravb_set_delay_mode(struct net_device *ndev)
+static void ravb_parse_delay_mode(struct net_device *ndev)
 {
 	struct ravb_private *priv = netdev_priv(ndev);
-	int set = 0;
 
 	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
 	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
-		set |= APSR_DM_RDM;
+		priv->rxcidm = true;
 
 	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
 	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 		if (!WARN(soc_device_match(ravb_delay_mode_quirk_match),
 			  "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree",
 			  phy_modes(priv->phy_interface)))
-			set |= APSR_DM_TDM;
+			priv->txcidm = true;
 	}
+}
 
+static void ravb_set_delay_mode(struct net_device *ndev)
+{
+	struct ravb_private *priv = netdev_priv(ndev);
+	u32 set = 0;
+
+	if (priv->rxcidm)
+		set |= APSR_DM_RDM;
+	if (priv->txcidm)
+		set |= APSR_DM_TDM;
 	ravb_modify(ndev, APSR, APSR_DM, set);
 }
 
@@ -2116,8 +2125,10 @@ static int ravb_probe(struct platform_device *pdev)
 	/* Request GTI loading */
 	ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
 
-	if (priv->chip_id != RCAR_GEN2)
+	if (priv->chip_id != RCAR_GEN2) {
+		ravb_parse_delay_mode(ndev);
 		ravb_set_delay_mode(ndev);
+	}
 
 	/* Allocate descriptor base address table */
 	priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
-- 
2.17.1

[PATCH/RFC 3/5] ravb: Add support for explicit internal clock delay configuration

[Geert Uytterhoeven]

Some EtherAVB variants support internal clock delay configuration, which
can add larger delays than the delays that are typically supported by
the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
properties).

Historically, the EtherAVB driver configured these delays based on the
"rgmii-*id" PHY mode.  This caused issues with PHY drivers that
implement PHY internal delays properly[1].  Hence a backwards-compatible
workaround was added by masking the PHY mode[2].

Add proper support for explicit configuration of the MAC internal clock
delays using the new "renesas,[rt]xc-delay-ps" properties.
Fall back to the old handling if none of these properties is present.

[1] Commit bcf3440c6dd78bfe ("net: phy: micrel: add phy-mode support for
    the KSZ9031 PHY")
[2] Commit 9b23203c32ee02cd ("ravb: Mask PHY mode to avoid inserting
    delays twice").

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/net/ethernet/renesas/ravb.h      |  1 +
 drivers/net/ethernet/renesas/ravb_main.c | 35 ++++++++++++++++++------
 2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index e5ca12ce93c730a9..7453b17a37a2c8d0 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -1038,6 +1038,7 @@ struct ravb_private {
 	unsigned wol_enabled:1;
 	unsigned rxcidm:1;		/* RX Clock Internal Delay Mode */
 	unsigned txcidm:1;		/* TX Clock Internal Delay Mode */
+	unsigned rgmii_override:1;	/* Deprecated rgmii-*id behavior */
 	int num_tx_desc;		/* TX descriptors per packet */
 };
 
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index f326234d1940f43e..0582846bec7726b6 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -1034,11 +1034,7 @@ static int ravb_phy_init(struct net_device *ndev)
 		pn = of_node_get(np);
 	}
 
-	iface = priv->phy_interface;
-	if (priv->chip_id != RCAR_GEN2 && phy_interface_mode_is_rgmii(iface)) {
-		/* ravb_set_delay_mode() takes care of internal delay mode */
-		iface = PHY_INTERFACE_MODE_RGMII;
-	}
+	iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII : priv->phy_interface;
 	phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
 	of_node_put(pn);
 	if (!phydev) {
@@ -1967,20 +1963,41 @@ static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = {
 };
 
 /* Set tx and rx clock internal delay modes */
-static void ravb_parse_delay_mode(struct net_device *ndev)
+static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
 {
 	struct ravb_private *priv = netdev_priv(ndev);
+	bool explicit_delay = false;
+	u32 delay;
+
+	if (!of_property_read_u32(np, "renesas,rxc-delay-ps", &delay)) {
+		/* Valid values are 0 and 1800, according to DT bindings */
+		priv->rxcidm = !!delay;
+		explicit_delay = true;
+	}
+	if (!of_property_read_u32(np, "renesas,txc-delay-ps", &delay)) {
+		/* Valid values are 0 and 2000, according to DT bindings */
+		priv->txcidm = !!delay;
+		explicit_delay = true;
+	}
 
+	if (explicit_delay)
+		return;
+
+	/* Fall back to legacy rgmii-*id behavior */
 	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
-	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
+	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 		priv->rxcidm = true;
+		priv->rgmii_override = true;
+	}
 
 	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
 	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 		if (!WARN(soc_device_match(ravb_delay_mode_quirk_match),
 			  "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree",
-			  phy_modes(priv->phy_interface)))
+			  phy_modes(priv->phy_interface))) {
 			priv->txcidm = true;
+			priv->rgmii_override = true;
+		}
 	}
 }
 
@@ -2126,7 +2143,7 @@ static int ravb_probe(struct platform_device *pdev)
 	ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
 
 	if (priv->chip_id != RCAR_GEN2) {
-		ravb_parse_delay_mode(ndev);
+		ravb_parse_delay_mode(np, ndev);
 		ravb_set_delay_mode(ndev);
 	}
 
-- 
2.17.1

[PATCH/RFC 4/5] arm64: dts: renesas: rcar-gen3: Convert EtherAVB to explicit delay handling

[Geert Uytterhoeven]

Some EtherAVB variants support internal clock delay configuration, which
can add larger delays than the delays that are typically supported by
the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
properties).

Historically, the EtherAVB driver configured these delays based on the
"rgmii-*id" PHY mode.  This was wrong, as these are meant solely for the
PHY, not for the MAC.  Hence properties were introduced for explicit
configuration of these delays.

Convert the R-Car Gen3 DTS files from the old to the new scheme:
  - Add default "renesas,rxc-delay-ps" and "renesas,txc-delay-ps"
    properties to the SoC .dtsi files, to be overridden by board files
    where needed,
  - Convert board files from "rgmii-*id" PHY modes to "rgmii", adding
    the appropriate "renesas,rxc-delay-ps" and/or "renesas,txc-delay-ps"
    overrides.

Notes:
  - R-Car E3 and D3 do not support TX internal delay handling,
  - On R-Car D3, TX internal delay handling must always be enabled,
    hence this fixes a bug on Draak,
  - On R-Car V3H, RX internal delay handling must always be enabled.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on "[PATCH/RFC 3/5] ravb: Add support for explicit internal
clock delay configuration" and must not be applied before that
dependency has hit upstream.
---
 arch/arm64/boot/dts/renesas/r8a77951.dtsi        | 2 ++
 arch/arm64/boot/dts/renesas/r8a77960.dtsi        | 2 ++
 arch/arm64/boot/dts/renesas/r8a77961.dtsi        | 2 ++
 arch/arm64/boot/dts/renesas/r8a77965.dtsi        | 2 ++
 arch/arm64/boot/dts/renesas/r8a77970-eagle.dts   | 3 ++-
 arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts   | 3 ++-
 arch/arm64/boot/dts/renesas/r8a77970.dtsi        | 2 ++
 arch/arm64/boot/dts/renesas/r8a77980.dtsi        | 2 ++
 arch/arm64/boot/dts/renesas/r8a77990.dtsi        | 1 +
 arch/arm64/boot/dts/renesas/r8a77995.dtsi        | 1 +
 arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 +-
 arch/arm64/boot/dts/renesas/ulcb.dtsi            | 2 +-
 12 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
index 61d67d9714ab9531..c303bab0d6125351 100644
--- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
@@ -1250,6 +1250,8 @@
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			renesas,rxc-delay-ps = <0>;
+			renesas,txc-delay-ps = <0>;
 			iommus = <&ipmmu_ds0 16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
index 33bf62acffbb73d2..cabe38bb74dde7b9 100644
--- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
@@ -1126,6 +1126,8 @@
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			renesas,rxc-delay-ps = <0>;
+			renesas,txc-delay-ps = <0>;
 			iommus = <&ipmmu_ds0 16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
index 760e738b75b3da9a..1fd6412e7c2b0fce 100644
--- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
@@ -923,6 +923,8 @@
 			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			renesas,rxc-delay-ps = <0>;
+			renesas,txc-delay-ps = <0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 6f7ab39fd2824b46..bed63cbed490ce2d 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -988,6 +988,8 @@
 			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			renesas,rxc-delay-ps = <0>;
+			renesas,txc-delay-ps = <0>;
 			iommus = <&ipmmu_ds0 16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
index ac2156ab3e626174..88b3a78c796295fd 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
@@ -81,7 +81,8 @@
 
 	renesas,no-ether-link;
 	phy-handle = <&phy0>;
-	phy-mode = "rgmii-id";
+	renesas,rxc-delay-ps = <1800>;
+	renesas,txc-delay-ps = <2000>;
 	status = "okay";
 
 	phy0: ethernet-phy@0 {
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
index 01c4ba0f7be1caff..548e2b02f327ba45 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -102,7 +102,8 @@
 
 	renesas,no-ether-link;
 	phy-handle = <&phy0>;
-	phy-mode = "rgmii-id";
+	renesas,rxc-delay-ps = <1800>;
+	renesas,txc-delay-ps = <2000>;
 	status = "okay";
 
 	phy0: ethernet-phy@0 {
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index bd95ecb1b40d8f4d..c759396ffbe7e446 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -615,6 +615,8 @@
 			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			renesas,rxc-delay-ps = <0>;
+			renesas,txc-delay-ps = <0>;
 			iommus = <&ipmmu_rt 3>;
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 387e6d99f2f365f0..54bd6cbd30ee30e8 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -667,6 +667,8 @@
 			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			renesas,rxc-delay-ps = <0>;
+			renesas,txc-delay-ps = <2000>;
 			iommus = <&ipmmu_ds1 33>;
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 1932d79509ecc86c..9f969653af88f1e6 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -938,6 +938,7 @@
 			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			renesas,rxc-delay-ps = <0>;
 			iommus = <&ipmmu_ds0 16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index e5617ec0f49cb6de..d2d480514909ce02 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -628,6 +628,7 @@
 			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			renesas,rxc-delay-ps = <1800>;
 			iommus = <&ipmmu_ds0 16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 1b170ebcea87ef76..454c5c9d84723c13 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -330,7 +330,7 @@
 	pinctrl-0 = <&avb_pins>;
 	pinctrl-names = "default";
 	phy-handle = <&phy0>;
-	phy-mode = "rgmii-txid";
+	renesas,txc-delay-ps = <2000>;
 	status = "okay";
 
 	phy0: ethernet-phy@0 {
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index ff88af8e39d3fa10..1fcc0bf1870ecbde 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -144,7 +144,7 @@
 	pinctrl-0 = <&avb_pins>;
 	pinctrl-names = "default";
 	phy-handle = <&phy0>;
-	phy-mode = "rgmii-txid";
+	renesas,txc-delay-ps = <2000>;
 	status = "okay";
 
 	phy0: ethernet-phy@0 {
-- 
2.17.1

[PATCH/RFC 5/5] arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling

[Geert Uytterhoeven]

Some EtherAVB variants support internal clock delay configuration, which
can add larger delays than the delays that are typically supported by
the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
properties).

Historically, the EtherAVB driver configured these delays based on the
"rgmii-*id" PHY mode.  This was wrong, as these are meant solely for the
PHY, not for the MAC.  Hence properties were introduced for explicit
configuration of these delays.

Convert the RZ/G2 DTS files from the old to the new scheme:
  - Add default "renesas,rxc-delay-ps" and "renesas,txc-delay-ps"
    properties to the SoC .dtsi files, to be overridden by board files
    where needed,
  - Convert board files from "rgmii-*id" PHY modes to "rgmii", adding
    the appropriate "renesas,rxc-delay-ps" and/or "renesas,txc-delay-ps"
    overrides.

Notes:
  - RZ/G2E does not support TX internal delay handling.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on "[PATCH/RFC 3/5] ravb: Add support for explicit internal
clock delay configuration" and must not be applied before that
dependency has hit upstream.
---
 arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 2 +-
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi       | 2 ++
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi       | 2 ++
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi       | 1 +
 4 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
index acfcfd050a6cb2d5..c2ce2aaea6e6d64b 100644
--- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
@@ -19,7 +19,7 @@
 	pinctrl-0 = <&avb_pins>;
 	pinctrl-names = "default";
 	phy-handle = <&phy0>;
-	phy-mode = "rgmii-txid";
+	renesas,txc-delay-ps = <2000>;
 	status = "okay";
 
 	phy0: ethernet-phy@0 {
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 51a572898fd68a7d..192900c716990860 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1115,6 +1115,8 @@
 			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			renesas,rxc-delay-ps = <0>;
+			renesas,txc-delay-ps = <0>;
 			iommus = <&ipmmu_ds0 16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index b221f2575e6328f9..3e50541750e93f88 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -989,6 +989,8 @@
 			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			renesas,rxc-delay-ps = <0>;
+			renesas,txc-delay-ps = <0>;
 			iommus = <&ipmmu_ds0 16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 5c72a7efbb035d02..a478450090f20e0b 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -960,6 +960,7 @@
 			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			renesas,rxc-delay-ps = <0>;
 			iommus = <&ipmmu_ds0 16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.17.1

Re: [PATCH/RFC 1/5] dt-bindings: net: renesas,ravb: Document internal clock delay properties

[Oleksij Rempel]

Hi Geert,

Am 19.06.20 um 21:15 schrieb Geert Uytterhoeven:
> Some EtherAVB variants support internal clock delay configuration, which
> can add larger delays than the delays that are typically supported by
> the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
> properties).
>
> Add properties for configuring the internal MAC delays.
> These properties are mandatory, even when specified as zero, to
> distinguish between old and new DTBs.
>
> Update the example accordingly.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  .../devicetree/bindings/net/renesas,ravb.txt  | 29 ++++++++++---------
>  1 file changed, 16 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
> index 032b76f14f4fdb38..488ada78b6169b8e 100644
> --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
> +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
> @@ -64,6 +64,18 @@ Optional properties:
>  			 AVB_LINK signal.
>  - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
>  				 active-low instead of normal active-high.
> +- renesas,rxc-delay-ps: Internal RX clock delay.

may be it make sense to add a generic delay property for MACs and PHYs?

> +			This property is mandatory and valid only on R-Car Gen3
> +			and RZ/G2 SoCs.
> +			Valid values are 0 and 1800.
> +			A non-zero value is allowed only if phy-mode = "rgmii".
> +			Zero is not supported on R-Car D3.
> +- renesas,txc-delay-ps: Internal TX clock delay.
> +			This property is mandatory and valid only on R-Car H3,
> +			M3-W, M3-W+, M3-N, V3M, and V3H, and RZ/G2M and RZ/G2N.
> +			Valid values are 0 and 2000.

In the driver i didn't found sanity check for valid values.

> +			A non-zero value is allowed only if phy-mode = "rgmii".
> +			Zero is not supported on R-Car V3H.>  Example:
>
> @@ -105,8 +117,10 @@ Example:
>  				  "ch24";
>  		clocks = <&cpg CPG_MOD 812>;
>  		power-domains = <&cpg>;
> -		phy-mode = "rgmii-id";
> +		phy-mode = "rgmii";
>  		phy-handle = <&phy0>;
> +		renesas,rxc-delay-ps = <0>;
> +		renesas,txc-delay-ps = <2000>;
>
>  		pinctrl-0 = <&ether_pins>;
>  		pinctrl-names = "default";
> @@ -115,18 +129,7 @@ Example:
>  		#size-cells = <0>;
>
>  		phy0: ethernet-phy@0 {
> -			rxc-skew-ps = <900>;
> -			rxdv-skew-ps = <0>;
> -			rxd0-skew-ps = <0>;
> -			rxd1-skew-ps = <0>;
> -			rxd2-skew-ps = <0>;
> -			rxd3-skew-ps = <0>;
> -			txc-skew-ps = <900>;
> -			txen-skew-ps = <0>;
> -			txd0-skew-ps = <0>;
> -			txd1-skew-ps = <0>;
> -			txd2-skew-ps = <0>;
> -			txd3-skew-ps = <0>;
> +			rxc-skew-ps = <1500>;


I'm curios, how this numbers ware taken?
Old configurations was:
TX delay:
(txd*-skew-ps = 0) == -420ns
(txc-skew-ps = 900) == 0ns
resulting delays 0.420ns

RX delay:
(rxd*-skew-ps = 0) == -420ns
(rxc-skew-ps = 900) == 0ns
internal delay 1.2 + 420ns will be 1.62ns

I was not able to find actual delay values provided by the MAC. But from your patches it looks like 2ns.

So, end result will be:
TXID = 2.4ns
RXID = 3.62ns

Both values seems to be a bit out of spec. New values are:
TXID = PHY 0ns + MAC 2.0ns
RXID =
(rxd*-skew-ps = no change) == 0ns
(rxc-skew-ps = 1500) == +600ns
internal delay 1.2 + 600ns = 1.8ns

From the PHY point of view, it is RGMII_RXID mode. Are you sure, RGMII_ID is not working for you?
Till now the numbers was not looking as a fine tuning.
I assume, it is better to use proper phy-mode instead of skew-ps values. I feel like no one had time
to understand real configured values in this PHY.

>  			reg = <0>;
>  			interrupt-parent = <&gpio2>;
>  			interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
>


--
Regards,
Oleksij

Re: [PATCH/RFC 1/5] dt-bindings: net: renesas,ravb: Document internal clock delay properties

[Andrew Lunn]

On Sat, Jun 20, 2020 at 07:47:16AM +0200, Oleksij Rempel wrote:
> Hi Geert,
> 
> Am 19.06.20 um 21:15 schrieb Geert Uytterhoeven:
> > Some EtherAVB variants support internal clock delay configuration, which
> > can add larger delays than the delays that are typically supported by
> > the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
> > properties).
> >
> > Add properties for configuring the internal MAC delays.
> > These properties are mandatory, even when specified as zero, to
> > distinguish between old and new DTBs.
> >
> > Update the example accordingly.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> >  .../devicetree/bindings/net/renesas,ravb.txt  | 29 ++++++++++---------
> >  1 file changed, 16 insertions(+), 13 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
> > index 032b76f14f4fdb38..488ada78b6169b8e 100644
> > --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
> > +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
> > @@ -64,6 +64,18 @@ Optional properties:
> >  			 AVB_LINK signal.
> >  - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
> >  				 active-low instead of normal active-high.
> > +- renesas,rxc-delay-ps: Internal RX clock delay.
> 
> may be it make sense to add a generic delay property for MACs and PHYs?

See Dan Murphys "RGMII Internal delay common property" patchset. That
patchset is addressing the PHY side. Maybe we can build on that to
address the MAC side?

	Andrew

Re: [PATCH/RFC 1/5] dt-bindings: net: renesas,ravb: Document internal clock delay properties

[Sergei Shtylyov]

Hello!

On 06/19/2020 10:15 PM, Geert Uytterhoeven wrote:

> Some EtherAVB variants support internal clock delay configuration, which
> can add larger delays than the delays that are typically supported by
> the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
> properties).
> 
> Add properties for configuring the internal MAC delays.
> These properties are mandatory, even when specified as zero, to
> distinguish between old and new DTBs.
> 
> Update the example accordingly.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  .../devicetree/bindings/net/renesas,ravb.txt  | 29 ++++++++++---------
>  1 file changed, 16 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
> index 032b76f14f4fdb38..488ada78b6169b8e 100644
> --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
> +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
> @@ -64,6 +64,18 @@ Optional properties:
>  			 AVB_LINK signal.
>  - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
>  				 active-low instead of normal active-high.
> +- renesas,rxc-delay-ps: Internal RX clock delay.
> +			This property is mandatory and valid only on R-Car Gen3
> +			and RZ/G2 SoCs.
> +			Valid values are 0 and 1800.
> +			A non-zero value is allowed only if phy-mode = "rgmii".
> +			Zero is not supported on R-Car D3.

   Hm, where did you see about the D3 limitation?

> +- renesas,txc-delay-ps: Internal TX clock delay.
> +			This property is mandatory and valid only on R-Car H3,
> +			M3-W, M3-W+, M3-N, V3M, and V3H, and RZ/G2M and RZ/G2N.
> +			Valid values are 0 and 2000.
> +			A non-zero value is allowed only if phy-mode = "rgmii".
> +			Zero is not supported on R-Car V3H.

  Same question about V3H here...

[...]
> @@ -105,8 +117,10 @@ Example:
>  				  "ch24";
>  		clocks = <&cpg CPG_MOD 812>;
>  		power-domains = <&cpg>;
> -		phy-mode = "rgmii-id";
> +		phy-mode = "rgmii";
>  		phy-handle = <&phy0>;
> +		renesas,rxc-delay-ps = <0>;

   Mhm, zero RX delay in RGMII-ID mode?

> +		renesas,txc-delay-ps = <2000>;
>  
>  		pinctrl-0 = <&ether_pins>;
>  		pinctrl-names = "default";
> @@ -115,18 +129,7 @@ Example:
>  		#size-cells = <0>;
>  
>  		phy0: ethernet-phy@0 {
> -			rxc-skew-ps = <900>;
> -			rxdv-skew-ps = <0>;
> -			rxd0-skew-ps = <0>;
> -			rxd1-skew-ps = <0>;
> -			rxd2-skew-ps = <0>;
> -			rxd3-skew-ps = <0>;
> -			txc-skew-ps = <900>;
> -			txen-skew-ps = <0>;
> -			txd0-skew-ps = <0>;
> -			txd1-skew-ps = <0>;
> -			txd2-skew-ps = <0>;
> -			txd3-skew-ps = <0>;
> +			rxc-skew-ps = <1500>;

   Ah, you're relying on a PHY?

[...]

MBR, Sergei

Re: [PATCH/RFC 2/5] ravb: Split delay handling in parsing and applying

[Sergei Shtylyov]

On 06/19/2020 10:15 PM, Geert Uytterhoeven wrote:

> Currently, full delay handling is done in both the probe and resume
> paths.  Split it in two parts, so the resume path doesn't have to redo
> the parsing part over and over again.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

[...]

MBR, Sergei

Re: [PATCH/RFC 3/5] ravb: Add support for explicit internal clock delay configuration

[Sergei Shtylyov]

On 06/19/2020 10:15 PM, Geert Uytterhoeven wrote:

> Some EtherAVB variants support internal clock delay configuration, which
> can add larger delays than the delays that are typically supported by
> the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
> properties).
> 
> Historically, the EtherAVB driver configured these delays based on the
> "rgmii-*id" PHY mode.  This caused issues with PHY drivers that
> implement PHY internal delays properly[1].  Hence a backwards-compatible
> workaround was added by masking the PHY mode[2].
> 
> Add proper support for explicit configuration of the MAC internal clock
> delays using the new "renesas,[rt]xc-delay-ps" properties.
> Fall back to the old handling if none of these properties is present.
> 
> [1] Commit bcf3440c6dd78bfe ("net: phy: micrel: add phy-mode support for
>     the KSZ9031 PHY")
> [2] Commit 9b23203c32ee02cd ("ravb: Mask PHY mode to avoid inserting
>     delays twice").
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

> ---
>  drivers/net/ethernet/renesas/ravb.h      |  1 +
>  drivers/net/ethernet/renesas/ravb_main.c | 35 ++++++++++++++++++------
>  2 files changed, 27 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
> index e5ca12ce93c730a9..7453b17a37a2c8d0 100644
> --- a/drivers/net/ethernet/renesas/ravb.h
> +++ b/drivers/net/ethernet/renesas/ravb.h
> @@ -1038,6 +1038,7 @@ struct ravb_private {
>  	unsigned wol_enabled:1;
>  	unsigned rxcidm:1;		/* RX Clock Internal Delay Mode */
>  	unsigned txcidm:1;		/* TX Clock Internal Delay Mode */
> +	unsigned rgmii_override:1;	/* Deprecated rgmii-*id behavior */
>  	int num_tx_desc;		/* TX descriptors per packet */
>  };
>  
> diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
> index f326234d1940f43e..0582846bec7726b6 100644
> --- a/drivers/net/ethernet/renesas/ravb_main.c
> +++ b/drivers/net/ethernet/renesas/ravb_main.c
[...]
> @@ -1967,20 +1963,41 @@ static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = {
>  };
>  
>  /* Set tx and rx clock internal delay modes */
> -static void ravb_parse_delay_mode(struct net_device *ndev)
> +static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
>  {
>  	struct ravb_private *priv = netdev_priv(ndev);
> +	bool explicit_delay = false;
> +	u32 delay;
> +
> +	if (!of_property_read_u32(np, "renesas,rxc-delay-ps", &delay)) {
> +		/* Valid values are 0 and 1800, according to DT bindings */
> +		priv->rxcidm = !!delay;
> +		explicit_delay = true;
> +	}
> +	if (!of_property_read_u32(np, "renesas,txc-delay-ps", &delay)) {
> +		/* Valid values are 0 and 2000, according to DT bindings */
> +		priv->txcidm = !!delay;
> +		explicit_delay = true;
> +	}
>  
> +	if (explicit_delay)
> +		return;
> +
> +	/* Fall back to legacy rgmii-*id behavior */
>  	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
> -	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
> +	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
>  		priv->rxcidm = true;
> +		priv->rgmii_override = true;

   Mhm, these fields are not bool...

> +	}
>  
>  	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
>  	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
>  		if (!WARN(soc_device_match(ravb_delay_mode_quirk_match),
>  			  "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree",
> -			  phy_modes(priv->phy_interface)))
> +			  phy_modes(priv->phy_interface))) {
>  			priv->txcidm = true;
> +			priv->rgmii_override = true;

    Same here...

[...]

MBR, Sergei

Re: [PATCH/RFC 1/5] dt-bindings: net: renesas,ravb: Document internal clock delay properties

[Geert Uytterhoeven]

Hi Oleksij,

On Sat, Jun 20, 2020 at 7:47 AM Oleksij Rempel <linux@rempel-privat.de> wrote:
> Am 19.06.20 um 21:15 schrieb Geert Uytterhoeven:
> > Some EtherAVB variants support internal clock delay configuration, which
> > can add larger delays than the delays that are typically supported by
> > the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
> > properties).
> >
> > Add properties for configuring the internal MAC delays.
> > These properties are mandatory, even when specified as zero, to
> > distinguish between old and new DTBs.
> >
> > Update the example accordingly.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

> > --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
> > +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt

> > +                     This property is mandatory and valid only on R-Car Gen3
> > +                     and RZ/G2 SoCs.
> > +                     Valid values are 0 and 1800.
> > +                     A non-zero value is allowed only if phy-mode = "rgmii".
> > +                     Zero is not supported on R-Car D3.
> > +- renesas,txc-delay-ps: Internal TX clock delay.
> > +                     This property is mandatory and valid only on R-Car H3,
> > +                     M3-W, M3-W+, M3-N, V3M, and V3H, and RZ/G2M and RZ/G2N.
> > +                     Valid values are 0 and 2000.
>
> In the driver i didn't found sanity check for valid values.

As EtherAVB supports only zero and a single non-zero value, I didn't
bother validating the actual non-zero value in the driver.

However, I did implement full validation in the json-schema version of
the DT bindings, cfr. "[PATCH/RFC] dt-bindings: net: renesas,etheravb:
Convert to json-schema"
(https://lore.kernel.org/r/20200621081710.10245-1-geert+renesas@glider.be)
(In hindsight, I should not have postponed posting that patch)

> > @@ -105,8 +117,10 @@ Example:
> >                                 "ch24";
> >               clocks = <&cpg CPG_MOD 812>;
> >               power-domains = <&cpg>;
> > -             phy-mode = "rgmii-id";
> > +             phy-mode = "rgmii";
> >               phy-handle = <&phy0>;
> > +             renesas,rxc-delay-ps = <0>;
> > +             renesas,txc-delay-ps = <2000>;
> >
> >               pinctrl-0 = <&ether_pins>;
> >               pinctrl-names = "default";
> > @@ -115,18 +129,7 @@ Example:
> >               #size-cells = <0>;
> >
> >               phy0: ethernet-phy@0 {
> > -                     rxc-skew-ps = <900>;
> > -                     rxdv-skew-ps = <0>;
> > -                     rxd0-skew-ps = <0>;
> > -                     rxd1-skew-ps = <0>;
> > -                     rxd2-skew-ps = <0>;
> > -                     rxd3-skew-ps = <0>;
> > -                     txc-skew-ps = <900>;
> > -                     txen-skew-ps = <0>;
> > -                     txd0-skew-ps = <0>;
> > -                     txd1-skew-ps = <0>;
> > -                     txd2-skew-ps = <0>;
> > -                     txd3-skew-ps = <0>;
> > +                     rxc-skew-ps = <1500>;
>
>
> I'm curios, how this numbers ware taken?
> Old configurations was:
> TX delay:
> (txd*-skew-ps = 0) == -420ns
> (txc-skew-ps = 900) == 0ns
> resulting delays 0.420ns

Please ignore the actual contents of the old example.  It was based on a
very old DTS, which has received several fixes in the mean time.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH/RFC 1/5] dt-bindings: net: renesas,ravb: Document internal clock delay properties

[Geert Uytterhoeven]

Hi Sergei,

On Sat, Jun 20, 2020 at 8:16 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On 06/19/2020 10:15 PM, Geert Uytterhoeven wrote:
> > Some EtherAVB variants support internal clock delay configuration, which
> > can add larger delays than the delays that are typically supported by
> > the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
> > properties).
> >
> > Add properties for configuring the internal MAC delays.
> > These properties are mandatory, even when specified as zero, to
> > distinguish between old and new DTBs.
> >
> > Update the example accordingly.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

> > --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
> > +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
> > @@ -64,6 +64,18 @@ Optional properties:
> >                        AVB_LINK signal.
> >  - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
> >                                active-low instead of normal active-high.
> > +- renesas,rxc-delay-ps: Internal RX clock delay.
> > +                     This property is mandatory and valid only on R-Car Gen3
> > +                     and RZ/G2 SoCs.
> > +                     Valid values are 0 and 1800.
> > +                     A non-zero value is allowed only if phy-mode = "rgmii".
> > +                     Zero is not supported on R-Car D3.
>
>    Hm, where did you see about the D3 limitation?

R-Car Gen3 Hardware User's Manual, Section 50.2.7 ("AVB-DMAC Product
Specific Register (APSR)"), "RDM" bit:

    For R-Car D3, delayed mode is only available

> > +- renesas,txc-delay-ps: Internal TX clock delay.
> > +                     This property is mandatory and valid only on R-Car H3,
> > +                     M3-W, M3-W+, M3-N, V3M, and V3H, and RZ/G2M and RZ/G2N.
> > +                     Valid values are 0 and 2000.
> > +                     A non-zero value is allowed only if phy-mode = "rgmii".
> > +                     Zero is not supported on R-Car V3H.
>
>   Same question about V3H here...

Same section, "TDM" bit:

    For R-Car V3H, delayed mode is only available.

> > @@ -105,8 +117,10 @@ Example:
> >                                 "ch24";
> >               clocks = <&cpg CPG_MOD 812>;
> >               power-domains = <&cpg>;
> > -             phy-mode = "rgmii-id";
> > +             phy-mode = "rgmii";
> >               phy-handle = <&phy0>;
> > +             renesas,rxc-delay-ps = <0>;
>
>    Mhm, zero RX delay in RGMII-ID mode?

Please ignore the actual contents of the old example.  It was based on a
very old DTS, which has received several fixes in the mean time.

Should have written:

    Update the (bogus) example accordingly.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds