From: Lokesh Vutla <lokeshvutla@ti.com>
To: Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>, Nishanth Menon <nm@ti.com>,
Tero Kristo <t-kristo@ti.com>,
Santosh Shilimkar <ssantosh@kernel.org>,
Linux ARM Mailing List <linux-arm-kernel@lists.infradead.org>,
Sekhar Nori <nsekhar@ti.com>,
Grygorii Strashko <grygorii.strashko@ti.com>,
Peter Ujfalusi <peter.ujfalusi@ti.com>,
Device Tree Mailing List <devicetree@vger.kernel.org>,
Suman Anna <s-anna@ti.com>, Lokesh Vutla <lokeshvutla@ti.com>
Subject: [PATCH v5 05/10] dt-bindings: irqchip: Convert ti,sci-intr bindings to yaml
Date: Tue, 28 Jul 2020 10:47:30 +0530 [thread overview]
Message-ID: <20200728051735.6187-6-lokeshvutla@ti.com> (raw)
In-Reply-To: <20200728051735.6187-1-lokeshvutla@ti.com>
In order to automate the verification of DT nodes convert
ti,sci-intr.txt ti,sci-intr.yaml.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
.../interrupt-controller/ti,sci-intr.txt | 83 --------------
.../interrupt-controller/ti,sci-intr.yaml | 102 ++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 103 insertions(+), 84 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
deleted file mode 100644
index 8b56b2de1c73..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-Texas Instruments K3 Interrupt Router
-=====================================
-
-The Interrupt Router (INTR) module provides a mechanism to mux M
-interrupt inputs to N interrupt outputs, where all M inputs are selectable
-to be driven per N output. An Interrupt Router can either handle edge triggered
-or level triggered interrupts and that is fixed in hardware.
-
- Interrupt Router
- +----------------------+
- | Inputs Outputs |
- +-------+ | +------+ +-----+ |
- | GPIO |----------->| | irq0 | | 0 | | Host IRQ
- +-------+ | +------+ +-----+ | controller
- | . . | +-------+
- +-------+ | . . |----->| IRQ |
- | INTA |----------->| . . | +-------+
- +-------+ | . +-----+ |
- | +------+ | N | |
- | | irqM | +-----+ |
- | +------+ |
- | |
- +----------------------+
-
-There is one register per output (MUXCNTL_N) that controls the selection.
-Configuration of these MUXCNTL_N registers is done by a system controller
-(like the Device Memory and Security Controller on K3 AM654 SoC). System
-controller will keep track of the used and unused registers within the Router.
-Driver should request the system controller to get the range of GIC IRQs
-assigned to the requesting hosts. It is the drivers responsibility to keep
-track of Host IRQs.
-
-Communication between the host processor running an OS and the system
-controller happens through a protocol called TI System Control Interface
-(TISCI protocol). For more details refer:
-Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
-
-TISCI Interrupt Router Node:
-----------------------------
-Required Properties:
-- compatible: Must be "ti,sci-intr".
-- ti,intr-trigger-type: Should be one of the following:
- 1: If intr supports edge triggered interrupts.
- 4: If intr supports level triggered interrupts.
-- interrupt-controller: Identifies the node as an interrupt controller
-- #interrupt-cells: Specifies the number of cells needed to encode an
- interrupt source. The value should be 1.
- First cell should contain interrupt router input number
- as specified by hardware.
-- ti,sci: Phandle to TI-SCI compatible System controller node.
-- ti,sci-dev-id: TISCI device id of interrupt controller.
-- ti,interrupt-ranges: Set of triplets containing ranges that convert
- the INTR output interrupt numbers to parent's
- interrupt number. Each triplet has following entries:
- - First entry specifies the base for intr output irq
- - Second entry specifies the base for parent irqs
- - Third entry specifies the limit
-
-For more details on TISCI IRQ resource management refer:
-http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html
-
-Example:
---------
-The following example demonstrates both interrupt router node and the consumer
-node(main gpio) on the AM654 SoC:
-
-main_gpio_intr: interrupt-controller0 {
- compatible = "ti,sci-intr";
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <131>;
- ti,interrupt-ranges = <0 360 32>;
-};
-
-main_gpio0: gpio@600000 {
- ...
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
- ...
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
new file mode 100644
index 000000000000..cff6a956afb4
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 Interrupt Router
+
+maintainers:
+ - Lokesh Vutla <lokeshvutla@ti.com>
+
+allOf:
+ - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
+
+description: |
+ The Interrupt Router (INTR) module provides a mechanism to mux M
+ interrupt inputs to N interrupt outputs, where all M inputs are selectable
+ to be driven per N output. An Interrupt Router can either handle edge
+ triggered or level triggered interrupts and that is fixed in hardware.
+
+ Interrupt Router
+ +----------------------+
+ | Inputs Outputs |
+ +-------+ | +------+ +-----+ |
+ | GPIO |----------->| | irq0 | | 0 | | Host IRQ
+ +-------+ | +------+ +-----+ | controller
+ | . . | +-------+
+ +-------+ | . . |----->| IRQ |
+ | INTA |----------->| . . | +-------+
+ +-------+ | . +-----+ |
+ | +------+ | N | |
+ | | irqM | +-----+ |
+ | +------+ |
+ | |
+ +----------------------+
+
+ There is one register per output (MUXCNTL_N) that controls the selection.
+ Configuration of these MUXCNTL_N registers is done by a system controller
+ (like the Device Memory and Security Controller on K3 AM654 SoC). System
+ controller will keep track of the used and unused registers within the Router.
+ Driver should request the system controller to get the range of GIC IRQs
+ assigned to the requesting hosts. It is the drivers responsibility to keep
+ track of Host IRQs.
+
+ Communication between the host processor running an OS and the system
+ controller happens through a protocol called TI System Control Interface
+ (TISCI protocol).
+
+properties:
+ compatible:
+ const: ti,sci-intr
+
+ ti,intr-trigger-type:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 4]
+ description: |
+ Should be one of the following.
+ 1 = If intr supports edge triggered interrupts.
+ 4 = If intr supports level triggered interrupts.
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+ description: |
+ The 1st cell should contain interrupt router input hw number.
+
+ ti,interrupt-ranges:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ description: |
+ Interrupt ranges that converts the INTR output hw irq numbers
+ to parents's input interrupt numbers.
+ items:
+ items:
+ - description: |
+ "output_irq" specifies the base for intr output irq
+ - description: |
+ "parent's input irq" specifies the base for parent irq
+ - description: |
+ "limit" specifies the limit for translation
+
+required:
+ - compatible
+ - ti,intr-trigger-type
+ - interrupt-controller
+ - '#interrupt-cells'
+ - ti,sci
+ - ti,sci-dev-id
+ - ti,interrupt-ranges
+
+examples:
+ - |
+ main_gpio_intr: interrupt-controller0 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <131>;
+ ti,interrupt-ranges = <0 360 32>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index c76fd456aaba..bc88886c05c6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16919,7 +16919,7 @@ F: Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml
F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt
-F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
+F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt
F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
F: drivers/clk/keystone/sci-clk.c
--
2.27.0
next prev parent reply other threads:[~2020-07-28 5:18 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-28 5:17 [PATCH v5 00/10] irqchip: ti, sci-intr/inta: Update the dt bindings to accept different interrupt parents Lokesh Vutla
2020-07-28 5:17 ` [PATCH v5 01/10] firmware: ti_sci: Drop the device id to resource type translation Lokesh Vutla
2020-07-28 5:17 ` [PATCH v5 02/10] firmware: ti_sci: Drop unused structure ti_sci_rm_type_map Lokesh Vutla
2020-07-28 5:17 ` [PATCH v5 03/10] firmware: ti_sci: Add support for getting resource with subtype Lokesh Vutla
2020-07-28 5:17 ` [PATCH v5 04/10] dt-bindings: irqchip: ti,sci-intr: Update bindings to drop the usage of gic as parent Lokesh Vutla
2020-07-28 5:17 ` Lokesh Vutla [this message]
2020-07-28 5:17 ` [PATCH v5 06/10] irqchip/ti-sci-intr: Add support for INTR being a parent to INTR Lokesh Vutla
2020-07-28 5:17 ` [PATCH v5 07/10] dt-bindings: irqchip: ti,sci-inta: Update docs to support different parent Lokesh Vutla
2020-07-28 5:17 ` [PATCH v5 08/10] dt-bindings: irqchip: Convert ti,sci-inta bindings to yaml Lokesh Vutla
2020-07-28 5:17 ` [PATCH v5 09/10] irqchip/ti-sci-inta: Do not store TISCI device id in platform device id field Lokesh Vutla
2020-07-28 5:17 ` [PATCH v5 10/10] irqchip/ti-sci-inta: Add support for INTA directly connecting to GIC Lokesh Vutla
2020-07-31 17:01 ` [PATCH v5 00/10] irqchip: ti, sci-intr/inta: Update the dt bindings to accept different interrupt parents Marc Zyngier
2020-07-31 17:51 ` Lokesh Vutla
2020-07-31 18:16 ` Rob Herring
2020-07-31 18:24 ` Suman Anna
2020-07-31 20:59 ` Rob Herring
2020-08-02 10:34 ` Sekhar Nori
2020-08-04 17:16 ` Lokesh Vutla
2020-08-04 17:28 ` Sekhar Nori
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