* [PATCH v3 1/4] dt-bindings: mmc: Convert mtk-sd to json-schema
2020-09-30 8:31 [PATCH v3 0/4] Add mmc support for MT8192 SoC Wenbin Mei
@ 2020-09-30 8:31 ` Wenbin Mei
2020-10-05 12:41 ` Ulf Hansson
2020-09-30 8:31 ` [PATCH v3 2/4] mmc: dt-bindings: add support for MT8192 SoC Wenbin Mei
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Wenbin Mei @ 2020-09-30 8:31 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring
Cc: Chaotian Jing, Matthias Brugger, linux-mmc, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, srv_heupstream,
Wenbin Mei
Convert the mtk-sd binding to DT schema format using json-schema.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
---
.../devicetree/bindings/mmc/mtk-sd.txt | 75 --------
.../devicetree/bindings/mmc/mtk-sd.yaml | 168 ++++++++++++++++++
2 files changed, 168 insertions(+), 75 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt
create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.yaml
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
deleted file mode 100644
index 26a8f320a156..000000000000
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-* MTK MMC controller
-
-The MTK MSDC can act as a MMC controller
-to support MMC, SD, and SDIO types of memory cards.
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the msdc driver.
-
-Required properties:
-- compatible: value should be either of the following.
- "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
- "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
- "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
- "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
- "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
- "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
- "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
- "mediatek,mt7622-mmc": for MT7622 SoC
- "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
- "mediatek,mt7620-mmc", for MT7621 SoC (and others)
-
-- reg: physical base address of the controller and length
-- interrupts: Should contain MSDC interrupt number
-- clocks: Should contain phandle for the clock feeding the MMC controller
-- clock-names: Should contain the following:
- "source" - source clock (required)
- "hclk" - HCLK which used for host (required)
- "source_cg" - independent source clock gate (required for MT2712)
- "bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
-- pinctrl-names: should be "default", "state_uhs"
-- pinctrl-0: should contain default/high speed pin ctrl
-- pinctrl-1: should contain uhs mode pin ctrl
-- vmmc-supply: power to the Core
-- vqmmc-supply: power to the IO
-
-Optional properties:
-- assigned-clocks: PLL of the source clock
-- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
-- hs400-ds-delay: HS400 DS delay setting
-- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
- This field has total 32 stages.
- The value is an integer from 0 to 31.
-- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
- This field has total 32 stages.
- The value is an integer from 0 to 31.
-- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
- If present,HS400 command responses are sampled on rising edges.
- If not present,HS400 command responses are sampled on falling edges.
-- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
- error caused by stop clock(fifo full)
- Valid range = [0:0x7]. if not present, default value is 0.
- applied to compatible "mediatek,mt2701-mmc".
-- resets: Phandle and reset specifier pair to softreset line of MSDC IP.
-- reset-names: Should be "hrst".
-
-Examples:
-mmc0: mmc@11230000 {
- compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
- reg = <0 0x11230000 0 0x108>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
- vmmc-supply = <&mt6397_vemc_3v3_reg>;
- vqmmc-supply = <&mt6397_vio18_reg>;
- clocks = <&pericfg CLK_PERI_MSDC30_0>,
- <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
- clock-names = "source", "hclk";
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&mmc0_pins_default>;
- pinctrl-1 = <&mmc0_pins_uhs>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
- hs400-ds-delay = <0x14015>;
- mediatek,hs200-cmd-int-delay = <26>;
- mediatek,hs400-cmd-int-delay = <14>;
- mediatek,hs400-cmd-resp-sel-rising;
-};
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
new file mode 100644
index 000000000000..7f89cbdc52a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MTK MSDC Storage Host Controller Binding
+
+maintainers:
+ - Chaotian Jing <chaotian.jing@mediatek.com>
+ - Wenbin Mei <wenbin.mei@mediatek.com>
+
+allOf:
+ - $ref: mmc-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt2701-mmc
+ - mediatek,mt2712-mmc
+ - mediatek,mt6779-mmc
+ - mediatek,mt7620-mmc
+ - mediatek,mt7622-mmc
+ - mediatek,mt8135-mmc
+ - mediatek,mt8173-mmc
+ - mediatek,mt8183-mmc
+ - mediatek,mt8516-mmc
+ - items:
+ - const: mediatek,mt7623-mmc
+ - const: mediatek,mt2701-mmc
+
+ clocks:
+ description:
+ Should contain phandle for the clock feeding the MMC controller.
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: source clock (required).
+ - description: HCLK which used for host (required).
+ - description: independent source clock gate (required for MT2712).
+ - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
+
+ clock-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ - const: source
+ - const: hclk
+ - const: source_cg
+ - const: bus_clk
+
+ pinctrl-names:
+ items:
+ - const: default
+ - const: state_uhs
+
+ pinctrl-0:
+ description:
+ should contain default/high speed pin ctrl.
+ maxItems: 1
+
+ pinctrl-1:
+ description:
+ should contain uhs mode pin ctrl.
+ maxItems: 1
+
+ vmmc-supply:
+ description:
+ power to the Core.
+ maxItems: 1
+
+ vqmmc-supply:
+ description:
+ power to the IO.
+ maxItems: 1
+
+ assigned-clocks:
+ description:
+ PLL of the source clock.
+ maxItems: 1
+
+ assigned-clock-parents:
+ description:
+ parent of source clock, used for HS400 mode to get 400Mhz source clock.
+ maxItems: 1
+
+ hs400-ds-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ HS400 DS delay setting.
+ minimum: 0
+ maximum: 0xffffffff
+
+ mediatek,hs200-cmd-int-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ HS200 command internal delay setting.
+ This field has total 32 stages.
+ The value is an integer from 0 to 31.
+ minimum: 0
+ maximum: 31
+
+ mediatek,hs400-cmd-int-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ HS400 command internal delay setting.
+ This field has total 32 stages.
+ The value is an integer from 0 to 31.
+ minimum: 0
+ maximum: 31
+
+ mediatek,hs400-cmd-resp-sel-rising:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ HS400 command response sample selection.
+ If present, HS400 command responses are sampled on rising edges.
+ If not present, HS400 command responses are sampled on falling edges.
+
+ mediatek,latch-ck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
+ data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
+ if not present, default value is 0.
+ applied to compatible "mediatek,mt2701-mmc".
+ minimum: 0
+ maximum: 7
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: hrst
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8173-mmc";
+ reg = <0x11230000 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
+ vmmc-supply = <&mt6397_vemc_3v3_reg>;
+ vqmmc-supply = <&mt6397_vio18_reg>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0>,
+ <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
+ clock-names = "source", "hclk";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ hs400-ds-delay = <0x14015>;
+ mediatek,hs200-cmd-int-delay = <26>;
+ mediatek,hs400-cmd-int-delay = <14>;
+ mediatek,hs400-cmd-resp-sel-rising;
+ };
+
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v3 1/4] dt-bindings: mmc: Convert mtk-sd to json-schema
2020-09-30 8:31 ` [PATCH v3 1/4] dt-bindings: mmc: Convert mtk-sd to json-schema Wenbin Mei
@ 2020-10-05 12:41 ` Ulf Hansson
0 siblings, 0 replies; 8+ messages in thread
From: Ulf Hansson @ 2020-10-05 12:41 UTC (permalink / raw)
To: Wenbin Mei
Cc: Rob Herring, Chaotian Jing, Matthias Brugger, linux-mmc, DTML,
Linux ARM, moderated list:ARM/Mediatek SoC support,
Linux Kernel Mailing List, srv_heupstream
[...]
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> new file mode 100644
> index 000000000000..7f89cbdc52a5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -0,0 +1,168 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MTK MSDC Storage Host Controller Binding
> +
> +maintainers:
> + - Chaotian Jing <chaotian.jing@mediatek.com>
> + - Wenbin Mei <wenbin.mei@mediatek.com>
> +
> +allOf:
> + - $ref: mmc-controller.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - mediatek,mt2701-mmc
> + - mediatek,mt2712-mmc
> + - mediatek,mt6779-mmc
> + - mediatek,mt7620-mmc
> + - mediatek,mt7622-mmc
> + - mediatek,mt8135-mmc
> + - mediatek,mt8173-mmc
> + - mediatek,mt8183-mmc
> + - mediatek,mt8516-mmc
> + - items:
> + - const: mediatek,mt7623-mmc
> + - const: mediatek,mt2701-mmc
> +
> + clocks:
> + description:
> + Should contain phandle for the clock feeding the MMC controller.
> + minItems: 2
> + maxItems: 4
> + items:
> + - description: source clock (required).
> + - description: HCLK which used for host (required).
> + - description: independent source clock gate (required for MT2712).
> + - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
> +
> + clock-names:
> + minItems: 2
> + maxItems: 4
> + items:
> + - const: source
> + - const: hclk
> + - const: source_cg
> + - const: bus_clk
> +
> + pinctrl-names:
> + items:
> + - const: default
> + - const: state_uhs
> +
> + pinctrl-0:
> + description:
> + should contain default/high speed pin ctrl.
> + maxItems: 1
> +
> + pinctrl-1:
> + description:
> + should contain uhs mode pin ctrl.
> + maxItems: 1
> +
> + vmmc-supply:
> + description:
> + power to the Core.
> + maxItems: 1
> +
> + vqmmc-supply:
> + description:
> + power to the IO.
> + maxItems: 1
The vmmc and vqmmc are described in the mmc-controller.yaml, so
shouldn't be needed here.
> +
> + assigned-clocks:
> + description:
> + PLL of the source clock.
> + maxItems: 1
> +
> + assigned-clock-parents:
> + description:
> + parent of source clock, used for HS400 mode to get 400Mhz source clock.
> + maxItems: 1
> +
> + hs400-ds-delay:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + HS400 DS delay setting.
> + minimum: 0
> + maximum: 0xffffffff
> +
> + mediatek,hs200-cmd-int-delay:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + HS200 command internal delay setting.
> + This field has total 32 stages.
> + The value is an integer from 0 to 31.
> + minimum: 0
> + maximum: 31
> +
> + mediatek,hs400-cmd-int-delay:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + HS400 command internal delay setting.
> + This field has total 32 stages.
> + The value is an integer from 0 to 31.
> + minimum: 0
> + maximum: 31
> +
> + mediatek,hs400-cmd-resp-sel-rising:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + HS400 command response sample selection.
> + If present, HS400 command responses are sampled on rising edges.
> + If not present, HS400 command responses are sampled on falling edges.
> +
> + mediatek,latch-ck:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
> + data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
> + if not present, default value is 0.
> + applied to compatible "mediatek,mt2701-mmc".
> + minimum: 0
> + maximum: 7
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + const: hrst
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
According to the current bindings, the vmmc/vqmmc supplies and the
pinctrls are required as well. I assume you should add them here too!?
[...]
Kind regards
Uffe
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 2/4] mmc: dt-bindings: add support for MT8192 SoC
2020-09-30 8:31 [PATCH v3 0/4] Add mmc support for MT8192 SoC Wenbin Mei
2020-09-30 8:31 ` [PATCH v3 1/4] dt-bindings: mmc: Convert mtk-sd to json-schema Wenbin Mei
@ 2020-09-30 8:31 ` Wenbin Mei
2020-09-30 8:31 ` [PATCH v3 3/4] arm64: dts: mt8192: add mmc device node Wenbin Mei
2020-09-30 8:31 ` [PATCH v3 4/4] mmc: mediatek: Add subsys clock control for MT8192 msdc Wenbin Mei
3 siblings, 0 replies; 8+ messages in thread
From: Wenbin Mei @ 2020-09-30 8:31 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring
Cc: Chaotian Jing, Matthias Brugger, linux-mmc, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, srv_heupstream,
Wenbin Mei
MT8192 mmc host ip is compatible with MT8183.
Add support for this.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 7f89cbdc52a5..81d2951bfc37 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -29,26 +29,37 @@ properties:
- items:
- const: mediatek,mt7623-mmc
- const: mediatek,mt2701-mmc
+ - items:
+ - const: mediatek,mt8192-mmc
+ - const: mediatek,mt8183-mmc
clocks:
description:
Should contain phandle for the clock feeding the MMC controller.
minItems: 2
- maxItems: 4
+ maxItems: 8
items:
- description: source clock (required).
- description: HCLK which used for host (required).
- description: independent source clock gate (required for MT2712).
- description: bus clock used for internal register access (required for MT2712 MSDC0/3).
+ - description: msdc subsys clock gate (required for MT8192).
+ - description: peripheral bus clock gate (required for MT8192).
+ - description: AXI bus clock gate (required for MT8192).
+ - description: AHB bus clock gate (required for MT8192).
clock-names:
minItems: 2
- maxItems: 4
+ maxItems: 8
items:
- const: source
- const: hclk
- const: source_cg
- const: bus_clk
+ - const: sys_cg
+ - const: pclk_cg
+ - const: axi_cg
+ - const: ahb_cg
pinctrl-names:
items:
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 3/4] arm64: dts: mt8192: add mmc device node
2020-09-30 8:31 [PATCH v3 0/4] Add mmc support for MT8192 SoC Wenbin Mei
2020-09-30 8:31 ` [PATCH v3 1/4] dt-bindings: mmc: Convert mtk-sd to json-schema Wenbin Mei
2020-09-30 8:31 ` [PATCH v3 2/4] mmc: dt-bindings: add support for MT8192 SoC Wenbin Mei
@ 2020-09-30 8:31 ` Wenbin Mei
2020-09-30 8:31 ` [PATCH v3 4/4] mmc: mediatek: Add subsys clock control for MT8192 msdc Wenbin Mei
3 siblings, 0 replies; 8+ messages in thread
From: Wenbin Mei @ 2020-09-30 8:31 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring
Cc: Chaotian Jing, Matthias Brugger, linux-mmc, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, srv_heupstream,
Wenbin Mei
This commit adds mmc device node for mt8192
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 ++++++++
2 files changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 0205837fa698..a4279fa87c2b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -27,3 +28,91 @@
&uart0 {
status = "okay";
};
+
+&mmc0 {
+ status = "okay";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ supports-cqe;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ hs400-ds-delay = <0x12814>;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
+ non-removable;
+};
+
+&pio {
+ mmc0_pins_default: mmc0default {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strenth = <3>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0@0{
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strenth = <4>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_ds {
+ pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index faea0d97c2a9..de3d10c0eeef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -760,6 +760,40 @@
#clock-cells = <1>;
};
+ mmc0: mmc@11f60000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f60000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11f70000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f70000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
mfgcfg: syscon@13fbf000 {
compatible = "mediatek,mt8192-mfgcfg", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 4/4] mmc: mediatek: Add subsys clock control for MT8192 msdc
2020-09-30 8:31 [PATCH v3 0/4] Add mmc support for MT8192 SoC Wenbin Mei
` (2 preceding siblings ...)
2020-09-30 8:31 ` [PATCH v3 3/4] arm64: dts: mt8192: add mmc device node Wenbin Mei
@ 2020-09-30 8:31 ` Wenbin Mei
2020-10-01 6:14 ` Nicolas Boichat
3 siblings, 1 reply; 8+ messages in thread
From: Wenbin Mei @ 2020-09-30 8:31 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring
Cc: Chaotian Jing, Matthias Brugger, linux-mmc, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, srv_heupstream,
Wenbin Mei
MT8192 msdc is an independent sub system, we need control more bus
clocks for it.
Add support for the additional subsys clocks to allow it to be
configured appropriately.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
---
drivers/mmc/host/mtk-sd.c | 77 ++++++++++++++++++++++++++++++---------
1 file changed, 59 insertions(+), 18 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index a704745e5882..9a1422955593 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -425,6 +425,8 @@ struct msdc_host {
struct clk *h_clk; /* msdc h_clk */
struct clk *bus_clk; /* bus clock which used to access register */
struct clk *src_clk_cg; /* msdc source clock control gate */
+ struct clk *sys_clk_cg; /* msdc subsys clock control gate */
+ struct clk_bulk_data bulk_clks[3]; /* pclk, axi, ahb clock control gate */
u32 mclk; /* mmc subsystem clock frequency */
u32 src_clk_freq; /* source clock frequency */
unsigned char timing;
@@ -784,6 +786,8 @@ static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
static void msdc_gate_clock(struct msdc_host *host)
{
+ clk_bulk_disable_unprepare(ARRAY_SIZE(host->bulk_clks),
+ host->bulk_clks);
clk_disable_unprepare(host->src_clk_cg);
clk_disable_unprepare(host->src_clk);
clk_disable_unprepare(host->bus_clk);
@@ -792,10 +796,17 @@ static void msdc_gate_clock(struct msdc_host *host)
static void msdc_ungate_clock(struct msdc_host *host)
{
+ int ret;
+
clk_prepare_enable(host->h_clk);
clk_prepare_enable(host->bus_clk);
clk_prepare_enable(host->src_clk);
clk_prepare_enable(host->src_clk_cg);
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(host->bulk_clks),
+ host->bulk_clks);
+ if (ret)
+ dev_dbg(host->dev, "enable clks failed!\n");
+
while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
cpu_relax();
}
@@ -2366,6 +2377,52 @@ static void msdc_of_property_parse(struct platform_device *pdev,
host->cqhci = false;
}
+static int msdc_of_clock_parse(struct platform_device *pdev,
+ struct msdc_host *host)
+{
+ struct clk *clk;
+
+ host->src_clk = devm_clk_get(&pdev->dev, "source");
+ if (IS_ERR(host->src_clk))
+ return PTR_ERR(host->src_clk);
+
+ host->h_clk = devm_clk_get(&pdev->dev, "hclk");
+ if (IS_ERR(host->h_clk))
+ return PTR_ERR(host->h_clk);
+
+ host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
+ if (IS_ERR(host->bus_clk))
+ host->bus_clk = NULL;
+
+ /*source clock control gate is optional clock*/
+ host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
+ if (IS_ERR(host->src_clk_cg))
+ host->src_clk_cg = NULL;
+
+ host->sys_clk_cg = devm_clk_get(&pdev->dev, "sys_cg");
+ if (IS_ERR(host->sys_clk_cg))
+ host->sys_clk_cg = NULL;
+ else
+ clk_prepare_enable(host->sys_clk_cg);
+
+ clk = devm_clk_get(&pdev->dev, "pclk_cg");
+ if (IS_ERR(clk))
+ clk = NULL;
+ host->bulk_clks[0].clk = clk;
+
+ clk = devm_clk_get(&pdev->dev, "axi_cg");
+ if (IS_ERR(clk))
+ clk = NULL;
+ host->bulk_clks[1].clk = clk;
+
+ clk = devm_clk_get(&pdev->dev, "ahb_cg");
+ if (IS_ERR(clk))
+ clk = NULL;
+ host->bulk_clks[2].clk = clk;
+
+ return 0;
+}
+
static int msdc_drv_probe(struct platform_device *pdev)
{
struct mmc_host *mmc;
@@ -2405,25 +2462,9 @@ static int msdc_drv_probe(struct platform_device *pdev)
if (ret)
goto host_free;
- host->src_clk = devm_clk_get(&pdev->dev, "source");
- if (IS_ERR(host->src_clk)) {
- ret = PTR_ERR(host->src_clk);
- goto host_free;
- }
-
- host->h_clk = devm_clk_get(&pdev->dev, "hclk");
- if (IS_ERR(host->h_clk)) {
- ret = PTR_ERR(host->h_clk);
+ ret = msdc_of_clock_parse(pdev, host);
+ if (ret)
goto host_free;
- }
-
- host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
- if (IS_ERR(host->bus_clk))
- host->bus_clk = NULL;
- /*source clock control gate is optional clock*/
- host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
- if (IS_ERR(host->src_clk_cg))
- host->src_clk_cg = NULL;
host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
"hrst");
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v3 4/4] mmc: mediatek: Add subsys clock control for MT8192 msdc
2020-09-30 8:31 ` [PATCH v3 4/4] mmc: mediatek: Add subsys clock control for MT8192 msdc Wenbin Mei
@ 2020-10-01 6:14 ` Nicolas Boichat
2020-10-10 9:18 ` Wenbin Mei
0 siblings, 1 reply; 8+ messages in thread
From: Nicolas Boichat @ 2020-10-01 6:14 UTC (permalink / raw)
To: Wenbin Mei
Cc: Ulf Hansson, Rob Herring, Chaotian Jing, Matthias Brugger,
linux-mmc, Devicetree List, linux-arm Mailing List,
moderated list:ARM/Mediatek SoC support, lkml, srv_heupstream
On Wed, Sep 30, 2020 at 4:31 PM Wenbin Mei <wenbin.mei@mediatek.com> wrote:
>
> MT8192 msdc is an independent sub system, we need control more bus
> clocks for it.
> Add support for the additional subsys clocks to allow it to be
> configured appropriately.
>
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> ---
> drivers/mmc/host/mtk-sd.c | 77 ++++++++++++++++++++++++++++++---------
> 1 file changed, 59 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index a704745e5882..9a1422955593 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -425,6 +425,8 @@ struct msdc_host {
> struct clk *h_clk; /* msdc h_clk */
> struct clk *bus_clk; /* bus clock which used to access register */
> struct clk *src_clk_cg; /* msdc source clock control gate */
> + struct clk *sys_clk_cg; /* msdc subsys clock control gate */
> + struct clk_bulk_data bulk_clks[3]; /* pclk, axi, ahb clock control gate */
> u32 mclk; /* mmc subsystem clock frequency */
> u32 src_clk_freq; /* source clock frequency */
> unsigned char timing;
> @@ -784,6 +786,8 @@ static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
>
> static void msdc_gate_clock(struct msdc_host *host)
> {
> + clk_bulk_disable_unprepare(ARRAY_SIZE(host->bulk_clks),
> + host->bulk_clks);
> clk_disable_unprepare(host->src_clk_cg);
> clk_disable_unprepare(host->src_clk);
> clk_disable_unprepare(host->bus_clk);
> @@ -792,10 +796,17 @@ static void msdc_gate_clock(struct msdc_host *host)
>
> static void msdc_ungate_clock(struct msdc_host *host)
> {
> + int ret;
> +
> clk_prepare_enable(host->h_clk);
> clk_prepare_enable(host->bus_clk);
> clk_prepare_enable(host->src_clk);
> clk_prepare_enable(host->src_clk_cg);
> + ret = clk_bulk_prepare_enable(ARRAY_SIZE(host->bulk_clks),
> + host->bulk_clks);
> + if (ret)
> + dev_dbg(host->dev, "enable clks failed!\n");
dev_err looks a lot more appropriate. Also, don't you want to exit the
function in that case, rather than going to the while loop below where
you may get stuck?
> +
> while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
> cpu_relax();
> }
> @@ -2366,6 +2377,52 @@ static void msdc_of_property_parse(struct platform_device *pdev,
> host->cqhci = false;
> }
>
> +static int msdc_of_clock_parse(struct platform_device *pdev,
> + struct msdc_host *host)
> +{
> + struct clk *clk;
> +
> + host->src_clk = devm_clk_get(&pdev->dev, "source");
> + if (IS_ERR(host->src_clk))
> + return PTR_ERR(host->src_clk);
> +
> + host->h_clk = devm_clk_get(&pdev->dev, "hclk");
> + if (IS_ERR(host->h_clk))
> + return PTR_ERR(host->h_clk);
> +
> + host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
> + if (IS_ERR(host->bus_clk))
> + host->bus_clk = NULL;
Use devm_clk_get_optional instead (ditto for the next 2).
> +
> + /*source clock control gate is optional clock*/
> + host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
> + if (IS_ERR(host->src_clk_cg))
> + host->src_clk_cg = NULL;
> +
> + host->sys_clk_cg = devm_clk_get(&pdev->dev, "sys_cg");
> + if (IS_ERR(host->sys_clk_cg))
> + host->sys_clk_cg = NULL;
> + else
> + clk_prepare_enable(host->sys_clk_cg);
This doesn't need to be in an else branch, calling clk_prepare_enable
on a NULL clock is fine.
However, is it expected that this clock is turned on forever after
probe?! At the very least, the clock should be disabled in
msdc_drv_remove, but, really, I think it should be enabled as needed,
like the other clocks, in msdc_gate_clock?
> +
> + clk = devm_clk_get(&pdev->dev, "pclk_cg");
> + if (IS_ERR(clk))
> + clk = NULL;
> + host->bulk_clks[0].clk = clk;
> +
> + clk = devm_clk_get(&pdev->dev, "axi_cg");
> + if (IS_ERR(clk))
> + clk = NULL;
> + host->bulk_clks[1].clk = clk;
> +
> + clk = devm_clk_get(&pdev->dev, "ahb_cg");
> + if (IS_ERR(clk))
> + clk = NULL;
> + host->bulk_clks[2].clk = clk;
Use devm_clk_bulk_get_optional for these 3.
> +
> + return 0;
> +}
> +
> static int msdc_drv_probe(struct platform_device *pdev)
> {
> struct mmc_host *mmc;
> @@ -2405,25 +2462,9 @@ static int msdc_drv_probe(struct platform_device *pdev)
> if (ret)
> goto host_free;
>
> - host->src_clk = devm_clk_get(&pdev->dev, "source");
> - if (IS_ERR(host->src_clk)) {
> - ret = PTR_ERR(host->src_clk);
> - goto host_free;
> - }
> -
> - host->h_clk = devm_clk_get(&pdev->dev, "hclk");
> - if (IS_ERR(host->h_clk)) {
> - ret = PTR_ERR(host->h_clk);
> + ret = msdc_of_clock_parse(pdev, host);
> + if (ret)
> goto host_free;
> - }
> -
> - host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
> - if (IS_ERR(host->bus_clk))
> - host->bus_clk = NULL;
> - /*source clock control gate is optional clock*/
> - host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
> - if (IS_ERR(host->src_clk_cg))
> - host->src_clk_cg = NULL;
>
> host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
> "hrst");
> --
> 2.18.0
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v3 4/4] mmc: mediatek: Add subsys clock control for MT8192 msdc
2020-10-01 6:14 ` Nicolas Boichat
@ 2020-10-10 9:18 ` Wenbin Mei
0 siblings, 0 replies; 8+ messages in thread
From: Wenbin Mei @ 2020-10-10 9:18 UTC (permalink / raw)
To: Nicolas Boichat
Cc: Ulf Hansson, Rob Herring, Chaotian Jing, Matthias Brugger,
linux-mmc, Devicetree List, linux-arm Mailing List,
moderated list:ARM/Mediatek SoC support, lkml, srv_heupstream
On Thu, 2020-10-01 at 14:14 +0800, Nicolas Boichat wrote:
> On Wed, Sep 30, 2020 at 4:31 PM Wenbin Mei <wenbin.mei@mediatek.com> wrote:
> >
> > MT8192 msdc is an independent sub system, we need control more bus
> > clocks for it.
> > Add support for the additional subsys clocks to allow it to be
> > configured appropriately.
> >
> > Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> > ---
> > drivers/mmc/host/mtk-sd.c | 77 ++++++++++++++++++++++++++++++---------
> > 1 file changed, 59 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> > index a704745e5882..9a1422955593 100644
> > --- a/drivers/mmc/host/mtk-sd.c
> > +++ b/drivers/mmc/host/mtk-sd.c
> > @@ -425,6 +425,8 @@ struct msdc_host {
> > struct clk *h_clk; /* msdc h_clk */
> > struct clk *bus_clk; /* bus clock which used to access register */
> > struct clk *src_clk_cg; /* msdc source clock control gate */
> > + struct clk *sys_clk_cg; /* msdc subsys clock control gate */
> > + struct clk_bulk_data bulk_clks[3]; /* pclk, axi, ahb clock control gate */
> > u32 mclk; /* mmc subsystem clock frequency */
> > u32 src_clk_freq; /* source clock frequency */
> > unsigned char timing;
> > @@ -784,6 +786,8 @@ static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
> >
> > static void msdc_gate_clock(struct msdc_host *host)
> > {
> > + clk_bulk_disable_unprepare(ARRAY_SIZE(host->bulk_clks),
> > + host->bulk_clks);
> > clk_disable_unprepare(host->src_clk_cg);
> > clk_disable_unprepare(host->src_clk);
> > clk_disable_unprepare(host->bus_clk);
> > @@ -792,10 +796,17 @@ static void msdc_gate_clock(struct msdc_host *host)
> >
> > static void msdc_ungate_clock(struct msdc_host *host)
> > {
> > + int ret;
> > +
> > clk_prepare_enable(host->h_clk);
> > clk_prepare_enable(host->bus_clk);
> > clk_prepare_enable(host->src_clk);
> > clk_prepare_enable(host->src_clk_cg);
> > + ret = clk_bulk_prepare_enable(ARRAY_SIZE(host->bulk_clks),
> > + host->bulk_clks);
> > + if (ret)
> > + dev_dbg(host->dev, "enable clks failed!\n");
>
> dev_err looks a lot more appropriate. Also, don't you want to exit the
> function in that case, rather than going to the while loop below where
> you may get stuck?
>
I will change it in the next version.
> > +
> > while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
> > cpu_relax();
> > }
> > @@ -2366,6 +2377,52 @@ static void msdc_of_property_parse(struct platform_device *pdev,
> > host->cqhci = false;
> > }
> >
> > +static int msdc_of_clock_parse(struct platform_device *pdev,
> > + struct msdc_host *host)
> > +{
> > + struct clk *clk;
> > +
> > + host->src_clk = devm_clk_get(&pdev->dev, "source");
> > + if (IS_ERR(host->src_clk))
> > + return PTR_ERR(host->src_clk);
> > +
> > + host->h_clk = devm_clk_get(&pdev->dev, "hclk");
> > + if (IS_ERR(host->h_clk))
> > + return PTR_ERR(host->h_clk);
> > +
> > + host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
> > + if (IS_ERR(host->bus_clk))
> > + host->bus_clk = NULL;
>
> Use devm_clk_get_optional instead (ditto for the next 2).
>
> > +
> > + /*source clock control gate is optional clock*/
> > + host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
> > + if (IS_ERR(host->src_clk_cg))
> > + host->src_clk_cg = NULL;
> > +
> > + host->sys_clk_cg = devm_clk_get(&pdev->dev, "sys_cg");
> > + if (IS_ERR(host->sys_clk_cg))
> > + host->sys_clk_cg = NULL;
> > + else
> > + clk_prepare_enable(host->sys_clk_cg);
>
> This doesn't need to be in an else branch, calling clk_prepare_enable
> on a NULL clock is fine.
I will change it in the next version.
>
> However, is it expected that this clock is turned on forever after
> probe?! At the very least, the clock should be disabled in
> msdc_drv_remove, but, really, I think it should be enabled as needed,
> like the other clocks, in msdc_gate_clock?
>
This clock gate can not be closed, if it is closed, it can not be
accessed and can not be opened again.
So it is expected that this clock is turned on forever after probe.
> > +
> > + clk = devm_clk_get(&pdev->dev, "pclk_cg");
> > + if (IS_ERR(clk))
> > + clk = NULL;
> > + host->bulk_clks[0].clk = clk;
> > +
> > + clk = devm_clk_get(&pdev->dev, "axi_cg");
> > + if (IS_ERR(clk))
> > + clk = NULL;
> > + host->bulk_clks[1].clk = clk;
> > +
> > + clk = devm_clk_get(&pdev->dev, "ahb_cg");
> > + if (IS_ERR(clk))
> > + clk = NULL;
> > + host->bulk_clks[2].clk = clk;
>
> Use devm_clk_bulk_get_optional for these 3.
>
I will change it in the next version.
> > +
> > + return 0;
> > +}
> > +
> > static int msdc_drv_probe(struct platform_device *pdev)
> > {
> > struct mmc_host *mmc;
> > @@ -2405,25 +2462,9 @@ static int msdc_drv_probe(struct platform_device *pdev)
> > if (ret)
> > goto host_free;
> >
> > - host->src_clk = devm_clk_get(&pdev->dev, "source");
> > - if (IS_ERR(host->src_clk)) {
> > - ret = PTR_ERR(host->src_clk);
> > - goto host_free;
> > - }
> > -
> > - host->h_clk = devm_clk_get(&pdev->dev, "hclk");
> > - if (IS_ERR(host->h_clk)) {
> > - ret = PTR_ERR(host->h_clk);
> > + ret = msdc_of_clock_parse(pdev, host);
> > + if (ret)
> > goto host_free;
> > - }
> > -
> > - host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
> > - if (IS_ERR(host->bus_clk))
> > - host->bus_clk = NULL;
> > - /*source clock control gate is optional clock*/
> > - host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
> > - if (IS_ERR(host->src_clk_cg))
> > - host->src_clk_cg = NULL;
> >
> > host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
> > "hrst");
> > --
> > 2.18.0
^ permalink raw reply [flat|nested] 8+ messages in thread