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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id z25sm137745ood.21.2020.10.06.14.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Oct 2020 14:25:03 -0700 (PDT) Received: (nullmailer pid 2870551 invoked by uid 1000); Tue, 06 Oct 2020 21:25:02 -0000 Date: Tue, 6 Oct 2020 16:25:02 -0500 From: Rob Herring To: Martin Blumenstingl Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, bgolaszewski@baylibre.com, linus.walleij@linaro.org, linux-kernel@vger.kernel.org, bhelgaas@google.com Subject: Re: [RFC PATCH 2/3] dt-bindings: gpio: Add binding documentation for Etron EJ168/EJ188/EJ198 Message-ID: <20201006212502.GA2866970@bogus> References: <20201004162908.3216898-1-martin.blumenstingl@googlemail.com> <20201004162908.3216898-3-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201004162908.3216898-3-martin.blumenstingl@googlemail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sun, Oct 04, 2020 at 06:29:07PM +0200, Martin Blumenstingl wrote: > Etron EJ168/EJ188/EJ198 are USB xHCI host controllers which embed a GPIO > controller. > > Signed-off-by: Martin Blumenstingl > --- > .../devicetree/bindings/gpio/etron,ej1x8.yaml | 48 +++++++++++++++++++ > 1 file changed, 48 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml > > diff --git a/Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml b/Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml > new file mode 100644 > index 000000000000..fa554045bdb5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/etron,ej1x8.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: GPIO controller embedded into the EJ168/EJ188/EJ198 xHCI controllers > + > +maintainers: > + - Martin Blumenstingl > + > +properties: > + compatible: > + enum: > + - pci1b6f,7023 > + - pci1b6f,7052 > + > + reg: > + maxItems: 1 > + > + "#gpio-cells": > + const: 2 > + > + gpio-controller: true > + > +required: > + - compatible > + - reg > + - "#gpio-cells" > + - gpio-controller > + > +additionalProperties: false > + > +examples: > + - | > + pcie { > + #address-cells = <3>; > + #size-cells = <2>; > + > + gpio@0,0,0 { > + compatible = "pci1b6f,7023"; > + reg = <0x0 0x0 0x0 0x0 0x1000>; > + gpio-controller; > + #gpio-cells = <2>; > + }; How would this look if you needed to describe the XHCI controller? That's another PCI function? > + }; > + > +... > -- > 2.28.0 >