From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FD9EC41604 for ; Wed, 7 Oct 2020 20:57:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4057C20782 for ; Wed, 7 Oct 2020 20:57:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728542AbgJGU5j (ORCPT ); Wed, 7 Oct 2020 16:57:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726152AbgJGU5j (ORCPT ); Wed, 7 Oct 2020 16:57:39 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F462C061755 for ; Wed, 7 Oct 2020 13:57:39 -0700 (PDT) Received: from pty.hi.pengutronix.de ([2001:67c:670:100:1d::c5]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kQGVD-0002Sf-8D; Wed, 07 Oct 2020 22:57:35 +0200 Received: from ukl by pty.hi.pengutronix.de with local (Exim 4.89) (envelope-from ) id 1kQGVC-0001LM-Cl; Wed, 07 Oct 2020 22:57:34 +0200 Date: Wed, 7 Oct 2020 22:57:34 +0200 From: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= To: vijayakannan.ayyathurai@intel.com Cc: thierry.reding@gmail.com, robh+dt@kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, wan.ahmad.zainie.wan.mohamad@intel.com, andriy.shevchenko@linux.intel.com, mgross@linux.intel.com, lakshmi.bai.raja.subramanian@intel.com Subject: Re: [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay Message-ID: <20201007205734.vguookvp6wt3knuq@pengutronix.de> References: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="5e4jj4rnobifsvui" Content-Disposition: inline In-Reply-To: Autocrypt: addr=u.kleine-koenig@pengutronix.de; keydata= mQINBEwXmCYBEACoJSJcKIlkQcTYia0ymmMOBk2veFoy/a0LlqGUEjQ4WECBL19F2BYX1dSp5/Z dfKuV605usI6oq4x6k/LKmqZDl6YnqW/YmN/iZVCRunBRfvpTlL4lcNUu5Va/4GBRzBRrrrIhCI VL5zMV6hKywhHKTdOHVSZRftf+eRSBwENKXahmfOMDmekyf585etDPdzkFrLHNVFOCsFOU0gCK0 uVPyY0LH13eo4qEEMi88RCOfwYCFQqKXDdo41DWoDPB5OGCMaphIx9wC/nvtdcvMowsGde5iGgm HWK6sdC/O/xaV7fnz1sJzoJB1eT91LkGbdGxsLAT6nqlaNJiJtiBoRhscguVxVbn/I9mnUu7bLm TFBEAlaQGU/J7uQ4w94FXfosNGROt/otqltetMZlPbNvNhKnXv8U6eRyAP3ZMKTJa4hGr3UdYdt 4+MIiHcsANWp8T7oLYVxRbHPXPG49IURnhXUoGbscZmpptWcl29eboqCxL9n3KIyUT3ZB1xHbW3 Sk/Dqzf52tQOxZubzrpUJ8zaGIwYVUjfcPFwf3R3zrQvJq7mI4SddNIE8w3WJOPXDOYx7GjOa+I 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vijayakannan.ayyathurai@intel.com= wrote: > +static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *p= wm, > + const struct pwm_state *state) > +{ > + struct keembay_pwm *priv =3D to_keembay_pwm_dev(chip); > + struct pwm_state current_state; > + u16 pwm_h_count, pwm_l_count; > + unsigned long long div; > + unsigned long clk_rate; > + u32 pwm_count =3D 0; > + > + if (state->polarity !=3D PWM_POLARITY_NORMAL) > + return -ENOSYS; > + > + keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0, > + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); > + > + keembay_pwm_get_state(chip, pwm, ¤t_state); > + > + if (!state->enabled) { > + if (current_state.enabled) > + keembay_pwm_disable(priv, pwm->hwpwm); > + return 0; > + } > + > + /* > + * The upper 16 bits of the KMB_PWM_HIGHLOW_OFFSET register contain > + * the high time of the waveform, while the last 16 bits contain > + * the low time of the waveform, in terms of clock cycles. > + * > + * high time =3D clock rate * duty cycle > + * low time =3D clock rate * (period - duty cycle) > + */ > + > + clk_rate =3D clk_get_rate(priv->clk); > + /* Configure waveform high time */ > + div =3D clk_rate * state->duty_cycle; > + div =3D DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC); > + if (div > KMB_PWM_COUNT_MAX) > + return -ERANGE; > + > + pwm_h_count =3D div; > + /* Configure waveform low time */ > + div =3D clk_rate * (state->period - state->duty_cycle); > + div =3D DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC - pwm_h_count); In reply to your v7 I suggested the example: clk_rate =3D 333334 [Hz] state.duty_cycle =3D 1000500 [ns] state.period =3D 2001000 [ns] where the expected outcome is pwm_h_count =3D 333 pwm_l_count =3D 334 =2E Please reread my feedback there. I tried to construct an example where the value is more wrong, but with the constraint that pwm_h_count must be <=3D KMB_PWM_COUNT_MAX this isn't easy. The best I could come up with is: clk_rate =3D 1000000000 state.duty_cycle =3D 65535 [ns] state.period =3D 131070 [ns] where the right value for pwm_l_count is 65535 while you calculate 65539 (and then quit with -ERANGE). > + if (div > KMB_PWM_COUNT_MAX) > + return -ERANGE; > + > + pwm_l_count =3D div; > + > + pwm_count =3D FIELD_PREP(KMB_PWM_HIGH_MASK, pwm_h_count) | > + FIELD_PREP(KMB_PWM_LOW_MASK, pwm_l_count); > + > + writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm)); > + > + if (state->enabled && !current_state.enabled) > + keembay_pwm_enable(priv, pwm->hwpwm); > + > + return 0; > +} > + > +static const struct pwm_ops keembay_pwm_ops =3D { > + .owner =3D THIS_MODULE, > + .apply =3D keembay_pwm_apply, > + .get_state =3D keembay_pwm_get_state, > +}; > + > +static int keembay_pwm_probe(struct platform_device *pdev) > +{ > + struct device *dev =3D &pdev->dev; > + struct keembay_pwm *priv; > + int ret; > + > + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->clk =3D devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) > + return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n"); > + > + ret =3D clk_prepare_enable(priv->clk); > + if (ret) > + return ret; > + > + priv->base =3D devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(priv->base)) { > + clk_disable_unprepare(priv->clk); > + return PTR_ERR(priv->base); > + } > + > + priv->chip.base =3D -1; > + priv->chip.dev =3D dev; > + priv->chip.ops =3D &keembay_pwm_ops; > + priv->chip.npwm =3D KMB_TOTAL_PWM_CHANNELS; > + > + ret =3D pwmchip_add(&priv->chip); > + if (ret) { > + dev_err(dev, "Failed to add PWM chip: %pe\n", ERR_PTR(ret)); > + clk_disable_unprepare(priv->clk); > + return ret; > + } > + > + platform_set_drvdata(pdev, priv); > + > + return 0; > +} > + > +static int keembay_pwm_remove(struct platform_device *pdev) > +{ > + struct keembay_pwm *priv =3D platform_get_drvdata(pdev); > + > + clk_disable_unprepare(priv->clk); > + > + return pwmchip_remove(&priv->chip); You have to call pwmchip_remove first. Otherwise you're stopping the PWM while the framework still believes everything to be fine. > +} Best regards Uwe --=20 Pengutronix e.K. | Uwe Kleine-K=F6nig | Industrial Linux Solutions | https://www.pengutronix.de/ | --5e4jj4rnobifsvui Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEfnIqFpAYrP8+dKQLwfwUeK3K7AkFAl9+K7oACgkQwfwUeK3K 7AnkSAf/WMAGErAAZ6G7l5oJUo2RRbVtkiryg8uZ8pTIoFPGtmaZFZY9gkNs/sSr FbH6Jw6dQiNYsAZYvbPOUY3AyauGgV+w/1PcQ5bOAeLVIOJSq04R8eeJU8zNcEbj DjThbF4JfZ24DCbdNBg3m0wMxPYzfJIchk7P0yYlLpan0sXE8pz9wGc0HtIuGe06 wrqbyW/22XRpdxnTMqJ9q0wt6ZZXDN35YDbb57omSqEZthi2HgkC4QwVNkflwtyt pMTA2XLDK0If7iYC8MXeR+CU9vy4/RQFrEDmqSo0E7VAfPW2QTFl6NCBUOr7bUV3 7YMdlfOYKLWhcBRFbGx3Uctiv4f/CQ== =qpLg -----END PGP SIGNATURE----- --5e4jj4rnobifsvui--