From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9642C433E7 for ; Thu, 8 Oct 2020 00:26:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 840D52076B for ; Thu, 8 Oct 2020 00:26:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726361AbgJHA0Z (ORCPT ); Wed, 7 Oct 2020 20:26:25 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:48936 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726129AbgJHA0Z (ORCPT ); Wed, 7 Oct 2020 20:26:25 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kQJlF-000cLX-2X; Thu, 08 Oct 2020 02:26:21 +0200 Date: Thu, 8 Oct 2020 02:26:21 +0200 From: Andrew Lunn To: Vivek Unune Cc: devicetree@vger.kernel.org, Hauke Mehrtens , =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= , linux-kernel@vger.kernel.org, Rob Herring , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl Message-ID: <20201008002621.GF112961@lunn.ch> References: <6687de05226dd055ee362933d4841a12b038792d.1601655904.git.npcomplete13@gmail.com> <20201007210134.GD112961@lunn.ch> <20201007214633.GA1972@ubuntu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201007214633.GA1972@ubuntu> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Oct 07, 2020 at 05:46:33PM -0400, Vivek Unune wrote: > On Wed, Oct 07, 2020 at 11:01:34PM +0200, Andrew Lunn wrote: > > On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote: > > > Forgo the use of mmioreg mdio mux infavor of the pinctrl > > > > Hi Vivek > > > > Could you add some more details please. I don't know this > > hardware. I'm assuming there are two MDIO busses, external as talked > > about in the comments, and an internal one? And for this hardware you > > only need one of them? But i don't see what pinmux has to do with > > this? > Hi Andrew, > > There are indeed two mdio busses. To access the external bus, 9th bit > of the mdio register has to be set. And to enable mii function, > one has to set the registers 6 & 7 which is part of the pin controller. > Earlier the pin controller was not defined and I resorted to use a > combination of memory mapped io mux to change desired bits. > > Now that we have a pin controller - which is resposnsible for other > functionality such as pwm, i2c, uart2, it makes sense to have a consistent > device tree What makes it confusing is that you make multiple changes at once. It would be easier to follow if you added the pinmux and removed the mmioreg mux, and move the switch into the mdio-bus-mux node. Then in a second patch rearrange the mdio-bus-mux. Small simple steps, with good commit messages are much easier to follow and say, Yes, this is correct. Andrew