From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4819FC4363A for ; Mon, 26 Oct 2020 10:56:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 08F2C22404 for ; Mon, 26 Oct 2020 10:56:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1771867AbgJZK4Y (ORCPT ); Mon, 26 Oct 2020 06:56:24 -0400 Received: from inva020.nxp.com ([92.121.34.13]:40126 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1771859AbgJZK4Y (ORCPT ); Mon, 26 Oct 2020 06:56:24 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 8A9551A0A73; Mon, 26 Oct 2020 11:56:22 +0100 (CET) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 7D1B61A0A0F; Mon, 26 Oct 2020 11:56:22 +0100 (CET) Received: from localhost (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 68BB920308; Mon, 26 Oct 2020 11:56:22 +0100 (CET) Date: Mon, 26 Oct 2020 12:56:22 +0200 From: Abel Vesa To: Lucas Stach Cc: Shawn Guo , Rob Herring , NXP Linux Team , Fabio Estevam , Frieder Schrempf , Marek Vasut , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: Re: [PATCH 10/11] arm64: dts: imx8mm: add GPC node and power domains Message-ID: <20201026105622.iqt6cej3iqog57jd@fsr-ub1664-175> References: <20200930155006.535712-1-l.stach@pengutronix.de> <20200930155006.535712-11-l.stach@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200930155006.535712-11-l.stach@pengutronix.de> User-Agent: NeoMutt/20180622 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 20-09-30 17:50:05, Lucas Stach wrote: > This adds the DT nodes to describe the power domains available on the > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > domain setups, as there is now a hierarchy of domains where complete > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also > fine granular gating within those subsystems is possible. > > Note that this is still incomplete, as both VPU and DISP domains are > missing their reset clocks. Those aren't directly sourced from the CCM, > but have another level of clock gating in the BLKCTL of those domains, > which needs a separate driver. > > Signed-off-by: Lucas Stach > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++ > 1 file changed, 57 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 76f040e4be5e..a841fb2d0458 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -4,6 +4,8 @@ > */ > > #include > +#include > +#include Needs to be imx8mm-reset.h, as in 8MM, not 8MQ. > #include > #include > #include > @@ -547,6 +549,61 @@ > interrupts = ; > #reset-cells = <1>; > }; > + > + gpc: gpc@303a0000 { > + compatible = "fsl,imx8mm-gpc"; > + reg = <0x303a0000 0x10000>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + #interrupt-cells = <3>; > + > + pgc { > + #address-cells = <1>; > + #size-cells = <0>; > + > + pgc_hsiomix: power-domain@0 { > + #power-domain-cells = <0>; > + reg = ; > + clocks = <&clk IMX8MM_CLK_USB_BUS>; > + }; > + > + pgc_pcie: power-domain@1 { > + #power-domain-cells = <0>; > + reg = ; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_otg1: power-domain@2 { > + #power-domain-cells = <0>; > + reg = ; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_otg2: power-domain@3 { > + #power-domain-cells = <0>; > + reg = ; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_gpumix: power-domain@4 { > + #power-domain-cells = <0>; > + reg = ; > + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MM_CLK_GPU_AHB>; > + }; > + > + pgc_gpu: power-domain@5 { > + #power-domain-cells = <0>; > + reg = ; > + clocks = <&clk IMX8MM_CLK_GPU_AHB>, > + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MM_CLK_GPU2D_ROOT>, > + <&clk IMX8MM_CLK_GPU3D_ROOT>; > + resets = <&src IMX8MQ_RESET_GPU_RESET>; > + power-domains = <&pgc_gpumix>; > + }; > + }; > + }; > }; > > aips2: bus@30400000 { > -- > 2.20.1 >