From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6039EC4363A for ; Tue, 27 Oct 2020 08:54:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 22E46207DE for ; Tue, 27 Oct 2020 08:54:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603788864; bh=CsoM0AEgwvLsKHr0ZMDCjtTRgkzvE3qeyp+nM1UlaW8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=v/FI5VomDVpsduR3vGfC1R9az93u+tj9iRQF40NVuxYIFg0neqzG77wbmrFP4RnnV N9Ln9CZ2iZ6VkeTQMV4DeYYkPZqDFylWrbcBOeSZRylM+iYnrbvI0P6q/hMAABCj5c zCwZZ4AaBs9xJs0qXozTfReLgcR0bohZ7O40Fnco= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2895138AbgJ0IyX (ORCPT ); Tue, 27 Oct 2020 04:54:23 -0400 Received: from mail-ej1-f67.google.com ([209.85.218.67]:39919 "EHLO mail-ej1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2895135AbgJ0IyX (ORCPT ); Tue, 27 Oct 2020 04:54:23 -0400 Received: by mail-ej1-f67.google.com with SMTP id bn26so1068738ejb.6; Tue, 27 Oct 2020 01:54:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=pl76InKLYF2UwW9waAthO63zpy2TGEsyyfIicHpInyw=; b=kieuVls0MHnoY8T0ezMslg13UBPaOt5M1Jk1huNNVh5v1BfM8JHT7UabQX8UFvo/4m hAbDT3ky7mV/dKYx3a7l2ttWH2LlJe5ZDXh6BR7XhxzwyHwmbv28ZhFYvvAEwZVfRFKC CcVlc9O4w88D/O1LDMy5Qul/E8ecJtuxNxHtlMiWpmLNsy0290qz64N5jaebap3q/HUR eZZvxw6WkyJALTPJR3FImcmQxjGhQVEs5F94kmCRxb1L6AlUrAr7H/5I+aeGUocgEFqX wHN/5wFVgTusCA+TeuYNZFTqOEiRW//DmprNSt7nPMxCgrN7fcnzmCecUuN9EGoKWKZr chsw== X-Gm-Message-State: AOAM531ig2VoO4phRloNS5AKclnBodDOXXONqv/igzRU2qoqTmoR+Laj XAha6rU8hq63TRVYzDJYas8= X-Google-Smtp-Source: ABdhPJzmpTJ+ZcG8BezO09PSRSuSnCiQ/tWevDipQfx8F299/Gs4qAXSPmuMp8sWXOngl8h7jPxqAw== X-Received: by 2002:a17:906:23f2:: with SMTP id j18mr1312596ejg.526.1603788861157; Tue, 27 Oct 2020 01:54:21 -0700 (PDT) Received: from kozik-lap ([194.230.155.184]) by smtp.googlemail.com with ESMTPSA id p9sm574643ejo.75.2020.10.27.01.54.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2020 01:54:20 -0700 (PDT) Date: Tue, 27 Oct 2020 09:54:17 +0100 From: Krzysztof Kozlowski To: Dmitry Osipenko Cc: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: Re: [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Message-ID: <20201027085417.GD4244@kozik-lap> References: <20201025221735.3062-1-digetx@gmail.com> <20201025221735.3062-5-digetx@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20201025221735.3062-5-digetx@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Oct 26, 2020 at 01:16:47AM +0300, Dmitry Osipenko wrote: > Tegra20 External Memory Controller talks to DRAM chips and it needs to be > reprogrammed when memory frequency changes. Tegra Memory Controller sits > behind EMC and these controllers are tightly coupled. This patch adds the > new phandle property which allows to properly express connection of EMC > and MC hardware in a device-tree, it also put the Tegra20 EMC binding on > par with Tegra30+ EMC bindings, which is handy to have. > > Signed-off-by: Dmitry Osipenko > --- > .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt > index 567cffd37f3f..1b0d4417aad8 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt > @@ -12,6 +12,7 @@ Properties: > irrespective of ram-code configuration. > - interrupts : Should contain EMC General interrupt. > - clocks : Should contain EMC clock. > +- nvidia,memory-controller : Phandle of the Memory Controller node. It looks like you adding a required property which is an ABI break. Best regards, Krzysztof