From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDE9CC4363A for ; Tue, 27 Oct 2020 19:34:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8448C2224E for ; Tue, 27 Oct 2020 19:34:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603827266; bh=W7z9oO4f0DaOqLVArVQpsTTVXB9kh0QtP2XTIc9SBAo=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=1M4vHxQvcGNCHDLY99GsOT7DH+EkD3/dt0As7FhTQNJc6n3ypEiadhYhQeJ5iTfHw LRITFddx3BNeIcUvDa+bXzrsj46/LqiFsdtL8A4HvGtlFFv/2rGDkGEdWIwNpSlw3k xf0IZHIbLR50j7qzmeD7y3QnqPXKkTvgHSRm5Uyw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2504063AbgJ0TeZ convert rfc822-to-8bit (ORCPT ); Tue, 27 Oct 2020 15:34:25 -0400 Received: from mail-ej1-f68.google.com ([209.85.218.68]:39449 "EHLO mail-ej1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2504048AbgJ0TeX (ORCPT ); Tue, 27 Oct 2020 15:34:23 -0400 Received: by mail-ej1-f68.google.com with SMTP id bn26so3903666ejb.6; Tue, 27 Oct 2020 12:34:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=nHvaL4wmpHKYi5m3WZBTUj9Yr645AuMpS/Lwjl+uNoA=; b=Z8496DmppCAr4Yo5LIfJT/Vy0N1RbQYfNm8zh9+tEay4I32IFICZBcBfkPajRlp80L z3AOMg03b4SLuUVml97mEKrZNNePC7in84d05dq/djr9frMVaD7U1ESwKGsjL4EDpRcT 1hBl0iYHv3iQHpg9DBm52jtnFuYhNyOEbKLkb5GEy9AOPfqC2wkgVO/BhXWhV58wjlvB Fj1xorF5VPzlrZ9En9ZUAoITyPKnpKrS5ZFvcbKhgfyyXwg+08i6+bAtMaiTRpYjVvFE jhf5GceHUDMEWRxcl+Q4yLwqt+cZ2YRkHrSsBr8FBbzcnlCuuXA5rQLLkKPm1nwjEg1E hGLQ== X-Gm-Message-State: AOAM530tEIzzlEfNWIS2YdprBhJT4D+xVS8dbscNeE3qlzY5JfDuiICb t3hXpnswX5yCwJWUGwTrgOkUEO6E6r36FS4X X-Google-Smtp-Source: ABdhPJzSfsy7j2DNep0zqEKUKGZS6bAlWA30JvZmU2UWtQoUwNW/pB7XvrPTG1y6Gt14VNHQQIvGHQ== X-Received: by 2002:a17:906:b204:: with SMTP id p4mr4185530ejz.214.1603827260969; Tue, 27 Oct 2020 12:34:20 -0700 (PDT) Received: from kozik-lap ([194.230.155.184]) by smtp.googlemail.com with ESMTPSA id r24sm1487476eds.67.2020.10.27.12.34.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2020 12:34:19 -0700 (PDT) Date: Tue, 27 Oct 2020 20:34:17 +0100 From: Krzysztof Kozlowski To: Dmitry Osipenko Cc: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: Re: [PATCH v6 05/52] dt-bindings: memory: tegra20: mc: Document new interconnect property Message-ID: <20201027193417.GB140636@kozik-lap> References: <20201025221735.3062-1-digetx@gmail.com> <20201025221735.3062-6-digetx@gmail.com> <20201027085548.GE4244@kozik-lap> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8BIT In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Oct 27, 2020 at 10:17:48PM +0300, Dmitry Osipenko wrote: > 27.10.2020 11:55, Krzysztof Kozlowski пишет: > > On Mon, Oct 26, 2020 at 01:16:48AM +0300, Dmitry Osipenko wrote: > >> Memory controller is interconnected with memory clients and with the > >> External Memory Controller. Document new interconnect property which > >> turns memory controller into interconnect provider. > >> > >> Acked-by: Rob Herring > >> Signed-off-by: Dmitry Osipenko > >> --- > >> .../bindings/memory-controllers/nvidia,tegra20-mc.txt | 3 +++ > >> 1 file changed, 3 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt > >> index e55328237df4..739b7c6f2e26 100644 > >> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt > >> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt > >> @@ -16,6 +16,8 @@ Required properties: > >> IOMMU specifier needed to encode an address. GART supports only a single > >> address space that is shared by all devices, therefore no additional > >> information needed for the address encoding. > >> +- #interconnect-cells : Should be 1. This cell represents memory client. > >> + The assignments may be found in header file . > > > > This is a list of required properties so you break the ABI. All existing > > DTBs will be affected. > > This is optional property for the older DTBs, but for newer DTs it's > mandatory. We do not consider here "older" or "newer" DTBs, but existing ones in the world using this binding. If it was optional so far, it cannot be made mandatory without changing the ABI. Which is an ABI break. > IIUC, it should be defined as a required property in the > binding. > > Please see tegra_mc_interconnect_setup() in "memory: tegra-mc: Add > interconnect framework", which check presence of the ICC DT property. The implementation indeed does not enforce it (except adding error msg, about which I commented). Therefore it should be an optional property. Best regards, Krzysztof