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From: Suman Anna <s-anna@ti.com>
To: Nishanth Menon <nm@ti.com>, Tero Kristo <t-kristo@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Suman Anna <s-anna@ti.com>
Subject: [PATCH 7/8] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to R5Fs
Date: Wed, 28 Oct 2020 22:38:01 -0500	[thread overview]
Message-ID: <20201029033802.15366-8-s-anna@ti.com> (raw)
In-Reply-To: <20201029033802.15366-1-s-anna@ti.com>

Add the required 'mboxes' property to all the R5F processors for the
TI J721E common processor board. The mailboxes and some shared memory
are required for running the Remote Processor Messaging (RPMsg) stack
between the host processor and each of the R5Fs. The nodes are therefore
added in the common k3-j721e-som-p0.dtsi file so that all of these can
be co-located.

The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.

Note that any R5F Core1 resources are needed and used only when that
R5F cluster is configured for Split-mode.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 26 ++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 5dc3ba739131..c48f4ffd1435 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 /dts-v1/;
@@ -208,6 +208,30 @@ &mailbox0_cluster11 {
 	status = "disabled";
 };
 
+&mcu_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+};
+
+&mcu_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+};
+
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+};
+
+&main_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+};
+
+&main_r5fss1_core0 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+};
+
+&main_r5fss1_core1 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+};
+
 &c66_0 {
 	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
 	memory-region = <&c66_0_dma_memory_region>,
-- 
2.28.0


  parent reply	other threads:[~2020-10-29 11:58 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-29  3:37 [PATCH 0/8] Add R5F nodes on TI K3 AM65x and J721E SoCs Suman Anna
2020-10-29  3:37 ` [PATCH 1/8] arm64: dts: ti: k3-am65-mcu: Add MCU domain R5F cluster node Suman Anna
2020-10-29  3:37 ` [PATCH 2/8] arm64: dts: ti: k3-am654-base-board: Add mailboxes to R5Fs Suman Anna
2020-10-29  3:37 ` [PATCH 3/8] arm64: dts: ti: k3-am654-base-board: Add DDR carveout memory nodes for R5Fs Suman Anna
2020-10-29  3:37 ` [PATCH 4/8] arm64: dts: ti: k3-am654-base-board: Reserve memory for IPC between R5F cores Suman Anna
2020-10-29  3:37 ` [PATCH 5/8] arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node Suman Anna
2020-10-29  3:38 ` [PATCH 6/8] arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes Suman Anna
2020-10-29  3:38 ` Suman Anna [this message]
2020-10-29  3:38 ` [PATCH 8/8] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for R5Fs Suman Anna
2020-11-06 11:43 ` [PATCH 0/8] Add R5F nodes on TI K3 AM65x and J721E SoCs Lokesh Vutla
2020-11-06 14:26   ` Suman Anna
2020-11-12 17:48 ` Nishanth Menon
2020-11-12 18:56   ` Suman Anna

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