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From: Frank Lee <frank@allwinnertech.com>
To: vkoul@kernel.org, robh+dt@kernel.org, mripard@kernel.org,
	wens@csie.org, ulf.hansson@linaro.org, kishon@ti.com,
	wim@linux-watchdog.org, linux@roeck-us.net,
	dan.j.williams@intel.com, linus.walleij@linaro.org,
	wsa+renesas@sang-engineering.com, dianders@chromium.org,
	marex@denx.de, colin.king@canonical.com, rdunlap@infradead.org,
	krzk@kernel.org, gregkh@linuxfoundation.org, megous@megous.com,
	rikard.falkeborn@gmail.com, dmaengine@vger.kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
	linux-watchdog@vger.kernel.org, linux-gpio@vger.kernel.org,
	tiny.windzz@gmail.com
Cc: Yangtao Li <frank@allwinnertech.com>
Subject: [PATCH 07/19] arm64: dts: allwinner: A100: Add PMU mode
Date: Tue, 10 Nov 2020 12:05:41 +0800	[thread overview]
Message-ID: <20201110040553.1381-8-frank@allwinnertech.com> (raw)
In-Reply-To: <20201110040553.1381-1-frank@allwinnertech.com>

From: Yangtao Li <frank@allwinnertech.com>

Add the Performance Monitoring Unit (PMU) device tree node to the A100
.dtsi, which tells DT users which interrupts are triggered by PMU overflow
events on each core.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index c34ed8045363..01ff53b5a7a8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -25,21 +25,21 @@ cpu0: cpu@0 {
 			enable-method = "psci";
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x1>;
 			enable-method = "psci";
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x2>;
 			enable-method = "psci";
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x3>;
@@ -47,6 +47,15 @@ cpu@3 {
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
-- 
2.28.0


  parent reply	other threads:[~2020-11-10  4:06 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-10  4:05 [PATCH 00/19] Second step support for A100 Frank Lee
2020-11-10  4:05 ` [PATCH 01/19] pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller Frank Lee
2020-11-10  4:05 ` [PATCH 02/19] pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON Frank Lee
2020-11-10  4:05 ` [PATCH 03/19] pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler Frank Lee
2020-11-10  4:05 ` [PATCH 04/19] dt-bindings: dma: allwinner,sun50i-a64-dma: Add A100 compatible Frank Lee
2020-11-10  4:05 ` [PATCH 05/19] dmaengine: sun6i: Add support for A100 DMA Frank Lee
2020-11-10  4:05 ` [PATCH 06/19] arm64: allwinner: a100: Add device node for DMA controller Frank Lee
2020-11-10  4:05 ` Frank Lee [this message]
2020-11-10  4:05 ` [PATCH 08/19] phy: sun4i-usb: remove enable_pmu_unk1 from sun50i_h6_cfg Frank Lee
2020-11-10  4:05 ` [PATCH 09/19] phy: allwinner: Convert to devm_platform_ioremap_* API Frank Lee
2020-11-10  6:00 ` [PATCH 00/19] Second step support for A100 Frank Lee
2020-11-10  8:43   ` Krzysztof Kozlowski
2020-11-10  8:51     ` Frank Lee
2020-11-10 12:48       ` Vinod Koul
2020-11-10 12:55         ` maxime

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