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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id cc8sm7811556edb.17.2020.12.06.02.37.18 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 06 Dec 2020 02:37:18 -0800 (PST) From: Johan Jonker To: heiko@sntech.de Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] ARM: dts: rockchip: add QoS register compatibles for rk3288 Date: Sun, 6 Dec 2020 11:37:09 +0100 Message-Id: <20201206103711.7465-2-jbx6244@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201206103711.7465-1-jbx6244@gmail.com> References: <20201206103711.7465-1-jbx6244@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org With the conversion of syscon.yaml minItems for compatibles was set to 2. Current Rockchip dtsi files only use "syscon" for QoS registers. Add Rockchip QoS compatibles for rk3288 to reduce notifications produced with: make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml Signed-off-by: Johan Jonker --- Changed v2: add space --- arch/arm/boot/dts/rk3288.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 68d5a58cf..01ea1f170 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1329,72 +1329,72 @@ }; qos_gpu_r: qos@ffaa0000 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffaa0000 0x0 0x20>; }; qos_gpu_w: qos@ffaa0080 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffaa0080 0x0 0x20>; }; qos_vio1_vop: qos@ffad0000 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0000 0x0 0x20>; }; qos_vio1_isp_w0: qos@ffad0100 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0100 0x0 0x20>; }; qos_vio1_isp_w1: qos@ffad0180 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0180 0x0 0x20>; }; qos_vio0_vop: qos@ffad0400 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0400 0x0 0x20>; }; qos_vio0_vip: qos@ffad0480 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0480 0x0 0x20>; }; qos_vio0_iep: qos@ffad0500 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0500 0x0 0x20>; }; qos_vio2_rga_r: qos@ffad0800 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0800 0x0 0x20>; }; qos_vio2_rga_w: qos@ffad0880 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0880 0x0 0x20>; }; qos_vio1_isp_r: qos@ffad0900 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffad0900 0x0 0x20>; }; qos_video: qos@ffae0000 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffae0000 0x0 0x20>; }; qos_hevc_r: qos@ffaf0000 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffaf0000 0x0 0x20>; }; qos_hevc_w: qos@ffaf0080 { - compatible = "syscon"; + compatible = "rockchip,rk3288-qos", "syscon"; reg = <0x0 0xffaf0080 0x0 0x20>; }; -- 2.11.0