From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5711FC433FE for ; Tue, 8 Dec 2020 18:13:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2688623B54 for ; Tue, 8 Dec 2020 18:13:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730953AbgLHSNK (ORCPT ); Tue, 8 Dec 2020 13:13:10 -0500 Received: from mga02.intel.com ([134.134.136.20]:27995 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730495AbgLHSNK (ORCPT ); Tue, 8 Dec 2020 13:13:10 -0500 IronPort-SDR: xdE8xuk9x4B79DJHW8VXOuDHi04ebZkd7eq0CsDykPa3IvRDu/ckHY5e2ikTKBJfZ0hjC1oW1c 2iDhO5skBB5g== X-IronPort-AV: E=McAfee;i="6000,8403,9829"; a="160993317" X-IronPort-AV: E=Sophos;i="5.78,403,1599548400"; d="scan'208";a="160993317" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2020 10:11:24 -0800 IronPort-SDR: /N7eHvVhIB2XWVuiGk32sRuWgu7ap1B1nX/UPdJmXK3+HP2qq1+d8fROUnqO50TNO0V//cEWH2 TL1oABWSQZqg== X-IronPort-AV: E=Sophos;i="5.78,403,1599548400"; d="scan'208";a="370477310" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2020 10:11:22 -0800 Received: from andy by smile with local (Exim 4.94) (envelope-from ) id 1kmhTM-00Cso6-6l; Tue, 08 Dec 2020 20:12:24 +0200 Date: Tue, 8 Dec 2020 20:12:24 +0200 From: Andy Shevchenko To: Rob Herring Cc: vijayakannan.ayyathurai@intel.com, daniel.lezcano@linaro.org, tglx@linutronix.de, devicetree@vger.kernel.org, mgross@linux.intel.com, wan.ahmad.zainie.wan.mohamad@intel.com, lakshmi.bai.raja.subramanian@intel.com Subject: Re: [PATCH v1 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC timer Message-ID: <20201208181224.GM4077@smile.fi.intel.com> References: <2938028520edbd0140805a22bdacd0b30c45b2df.1606377035.git.vijayakannan.ayyathurai@intel.com> <20201208161247.GA2620425@robh.at.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201208161247.GA2620425@robh.at.kernel.org> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Dec 08, 2020 at 10:12:47AM -0600, Rob Herring wrote: > On Thu, Nov 26, 2020 at 06:34:08PM +0800, vijayakannan.ayyathurai@intel.com wrote: > > From: Vijayakannan Ayyathurai > > > > Add Device Tree bindings for the Timer IP, which used as clocksource and > > clockevent in the Intel Keem Bay SoC. ... > > +examples: > > + - | > > + #include > > + #include > > + #define KEEM_BAY_A53_TIM > > + > > + timer@20330010 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x20330010 0xc>, > > + <0x20331000 0xc>; > > + interrupts = ; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + counter@203300e8 { > > + compatible = "intel,keembay-counter"; > > + reg = <0x203300e8 0xc>, > > + <0x20331000 0xc>; > > You have overlapping reg regions here. Don't do that. Define the DT > in terms of the h/w, not how you want to split things for Linux. > > It looks like a single h/w block providing multiple functions. Actually a good catch. Perhaps it needs to have a parent device that provides three resources (one common and one per each of two functions) and in the driver it should consume them accordingly. Though I'm not an expert in DT, does it sound correct from your perspective? > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; -- With Best Regards, Andy Shevchenko