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From: Shawn Guo <shawn.guo@linaro.org>
To: Stephen Boyd <sboyd@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Sivaprakash Murugesan <sivaprak@codeaurora.org>,
	Benjamin Li <benl@squareup.com>,
	devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-clk@vger.kernel.org, Shawn Guo <shawn.guo@linaro.org>
Subject: [PATCH 5/5] clk: qcom: a53-pll: Add MSM8939 a53pll clocks
Date: Tue,  4 May 2021 13:28:44 +0800	[thread overview]
Message-ID: <20210504052844.21096-6-shawn.guo@linaro.org> (raw)
In-Reply-To: <20210504052844.21096-1-shawn.guo@linaro.org>

It adds support for MSM8939 a53pll clock of Cluster0, Cluster1 and CCI
(Cache Coherent Interconnect).  The frequency data comes from vendor
kernel.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 drivers/clk/qcom/a53-pll.c | 42 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c
index bfa048dc01ec..8c6f8bcc6128 100644
--- a/drivers/clk/qcom/a53-pll.c
+++ b/drivers/clk/qcom/a53-pll.c
@@ -26,6 +26,45 @@ static const struct pll_freq_tbl msm8916_freq[] = {
 	{ }
 };
 
+static const struct pll_freq_tbl msm8939_c0_freq[] = {
+	{  998400000,  52, 0x0, 0x1, 0 },
+	{ 1113600000,  58, 0x0, 0x1, 0 },
+	{ 1209600000,  63, 0x0, 0x1, 0 },
+};
+
+static const struct pll_freq_tbl msm8939_c1_freq[] = {
+	{  652800000, 34, 0x0, 0x1, 0 },
+	{  691200000, 36, 0x0, 0x1, 0 },
+	{  729600000, 38, 0x0, 0x1, 0 },
+	{  806400000, 42, 0x0, 0x1, 0 },
+	{  844800000, 44, 0x0, 0x1, 0 },
+	{  883200000, 46, 0x0, 0x1, 0 },
+	{  960000000, 50, 0x0, 0x1, 0 },
+	{  998400000, 52, 0x0, 0x1, 0 },
+	{ 1036800000, 54, 0x0, 0x1, 0 },
+	{ 1113600000, 58, 0x0, 0x1, 0 },
+	{ 1209600000, 63, 0x0, 0x1, 0 },
+	{ 1190400000, 62, 0x0, 0x1, 0 },
+	{ 1267200000, 66, 0x0, 0x1, 0 },
+	{ 1344000000, 70, 0x0, 0x1, 0 },
+	{ 1363200000, 71, 0x0, 0x1, 0 },
+	{ 1420800000, 74, 0x0, 0x1, 0 },
+	{ 1459200000, 76, 0x0, 0x1, 0 },
+	{ 1497600000, 78, 0x0, 0x1, 0 },
+	{ 1536000000, 80, 0x0, 0x1, 0 },
+	{ 1574400000, 82, 0x0, 0x1, 0 },
+	{ 1612800000, 84, 0x0, 0x1, 0 },
+	{ 1632000000, 85, 0x0, 0x1, 0 },
+	{ 1651200000, 86, 0x0, 0x1, 0 },
+	{ 1689600000, 88, 0x0, 0x1, 0 },
+	{ 1708800000, 89, 0x0, 0x1, 0 },
+};
+
+static const struct pll_freq_tbl msm8939_cci_freq[] = {
+	{ 403200000, 21, 0x0, 0x1, 0 },
+	{ 595200000, 31, 0x0, 0x1, 0 },
+};
+
 static const struct regmap_config a53pll_regmap_config = {
 	.reg_bits		= 32,
 	.reg_stride		= 4,
@@ -98,6 +137,9 @@ static int qcom_a53pll_probe(struct platform_device *pdev)
 
 static const struct of_device_id qcom_a53pll_match_table[] = {
 	{ .compatible = "qcom,msm8916-a53pll", .data = msm8916_freq },
+	{ .compatible = "qcom,msm8939-a53pll-c0", .data = &msm8939_c0_freq },
+	{ .compatible = "qcom,msm8939-a53pll-c1", .data = &msm8939_c1_freq },
+	{ .compatible = "qcom,msm8939-a53pll-cci", .data = &msm8939_cci_freq },
 	{ }
 };
 
-- 
2.17.1


  parent reply	other threads:[~2021-05-04  5:29 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-04  5:28 [PATCH 0/5] Add MSM8939 APCS/A53PLL clock support Shawn Guo
2021-05-04  5:28 ` [PATCH 1/5] clk: qcom: apcs-msm8916: Flag a53mux instead of a53pll as critical Shawn Guo
2021-06-28  0:27   ` Stephen Boyd
2021-06-29  2:37     ` Shawn Guo
2021-05-04  5:28 ` [PATCH 2/5] dt-bindings: clock: update qcom,a53pll bindings for MSM8939 support Shawn Guo
2021-05-06 20:27   ` Rob Herring
2021-05-07  0:18     ` Shawn Guo
2021-05-04  5:28 ` [PATCH 3/5] clk: qcom: apcs-msm8916: Retrieve clock name from DT Shawn Guo
2021-06-28  0:28   ` Stephen Boyd
2021-06-29 13:36     ` Shawn Guo
2021-06-29 15:57       ` Bjorn Andersson
2021-06-29 20:23         ` Stephen Boyd
2021-06-29 20:39           ` Bjorn Andersson
2021-05-04  5:28 ` [PATCH 4/5] clk: qcom: a53-pll: Pass freq_tbl via match data Shawn Guo
2021-05-04  5:28 ` Shawn Guo [this message]
2021-06-28  0:24   ` [PATCH 5/5] clk: qcom: a53-pll: Add MSM8939 a53pll clocks Stephen Boyd
2021-06-21  6:37 ` [PATCH 0/5] Add MSM8939 APCS/A53PLL clock support Shawn Guo

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