From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D835C2B9F4 for ; Thu, 17 Jun 2021 19:09:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 54197613E1 for ; Thu, 17 Jun 2021 19:09:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233085AbhFQTLg (ORCPT ); Thu, 17 Jun 2021 15:11:36 -0400 Received: from mail.bugwerft.de ([46.23.86.59]:37030 "EHLO mail.bugwerft.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232671AbhFQTLb (ORCPT ); Thu, 17 Jun 2021 15:11:31 -0400 Received: from hq-00021.fritz.box (p57bc9ba2.dip0.t-ipconnect.de [87.188.155.162]) by mail.bugwerft.de (Postfix) with ESMTPSA id 4D08B4C20B2; Thu, 17 Jun 2021 19:09:20 +0000 (UTC) From: Daniel Mack To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, kuninori.morimoto.gx@renesas.com, mturquette@baylibre.com, sboyd@kernel.org, Daniel Mack Subject: [PATCH v3 5/9] clk: cs2000-cp: Make aux output function controllable Date: Thu, 17 Jun 2021 21:09:08 +0200 Message-Id: <20210617190912.262809-6-daniel@zonque.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617190912.262809-1-daniel@zonque.org> References: <20210617190912.262809-1-daniel@zonque.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The aux output pin can be configured to output either of the two clock inputs, the generated clock or the pll lock status. Allow access to this feature through a new optional device-tree property. Signed-off-by: Daniel Mack --- drivers/clk/clk-cs2000-cp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index 92bc4aca0f95..db7290621cef 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -39,6 +39,8 @@ /* DEVICE_CFG1 */ #define RSEL(x) (((x) & 0x3) << 3) #define RSEL_MASK RSEL(0x3) +#define AUXOUTSRC(x) (((x) & 0x3) << 1) +#define AUXOUTSRC_MASK AUXOUTSRC(0x3) #define ENDEV1 (0x1) /* DEVICE_CFG2 */ @@ -421,12 +423,19 @@ static int cs2000_clk_register(struct cs2000_priv *priv) struct clk_init_data init; const char *name = np->name; static const char *parent_names[CLK_MAX]; + u32 aux_out = 0; int ch = 0; /* it uses ch0 only at this point */ int rate; int ret; of_property_read_string(np, "clock-output-names", &name); + of_property_read_u32(np, "cirrus,aux-output-source", &aux_out); + ret = cs2000_bset(priv, DEVICE_CFG1, + AUXOUTSRC_MASK, AUXOUTSRC(aux_out)); + if (ret < 0) + return ret; + /* * set default rate as 1/1. * otherwise .set_rate which setup ratio -- 2.31.1