From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 458A8C2B9F4 for ; Mon, 28 Jun 2021 06:14:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 23AD461C2F for ; Mon, 28 Jun 2021 06:14:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230134AbhF1GQk (ORCPT ); Mon, 28 Jun 2021 02:16:40 -0400 Received: from mga07.intel.com ([134.134.136.100]:60982 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229778AbhF1GQj (ORCPT ); Mon, 28 Jun 2021 02:16:39 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10028"; a="271751092" X-IronPort-AV: E=Sophos;i="5.83,305,1616482800"; d="scan'208";a="271751092" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2021 23:14:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,305,1616482800"; d="scan'208";a="407607313" Received: from bspteam04.iind.intel.com ([10.106.46.142]) by orsmga006.jf.intel.com with ESMTP; 27 Jun 2021 23:14:11 -0700 From: shruthi.sanil@intel.com To: daniel.lezcano@linaro.org, tglx@linutronix.de, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: andriy.shevchenko@linux.intel.com, kris.pan@linux.intel.com, mgross@linux.intel.com, srikanth.thokala@intel.com, lakshmi.bai.raja.subramanian@intel.com, mallikarjunappa.sangannavar@intel.com, shruthi.sanil@intel.com Subject: [PATCH v4 0/2] Add the driver for Intel Keem Bay SoC timer block Date: Mon, 28 Jun 2021 11:44:08 +0530 Message-Id: <20210628061410.8009-1-shruthi.sanil@intel.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Shruthi Sanil The timer block supports 1 64-bit free running counter and 8 32-bit general purpose timers. Patch 1 holds the device tree binding documentation. Patch 2 holds the device driver. This driver is tested on the Keem Bay evaluation module board. Changes since v3: - Update in KConfig file to support COMPILE_TEST for Keem Bay timer. - Update in device tree bindings to remove status field. - Update in device tree bindings to remove 64-bit address space for the child nodes by using non-empty ranges. Changes since v2: - Add multi timer support. - Update in the device tree binding to support multi timers. - Code optimization. Changes since v1: - Add support for KEEMBAY_TIMER to get selected through Kconfig.platforms. - Add CLOCK_EVT_FEAT_DYNIRQ as part of clockevent feature. - Avoid overlapping reg regions across 2 device nodes. - Simplify 2 device nodes as 1 because both are from same IP block. - Adapt the driver code according to the new simplified devicetree. Shruthi Sanil (2): dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer clocksource: Add Intel Keem Bay timer support .../bindings/timer/intel,keembay-timer.yaml | 170 ++++++++++++ MAINTAINERS | 5 + drivers/clocksource/Kconfig | 11 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-keembay.c | 255 ++++++++++++++++++ 5 files changed, 442 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml create mode 100644 drivers/clocksource/timer-keembay.c base-commit: 62fb9874f5da54fdb243003b386128037319b219 -- 2.17.1