[PATCH v4 0/5] Misc Ingenic patches.

[PATCH v4 0/5] Misc Ingenic patches.

[周琰杰 (Zhou Yanjie)]

Some misc patches that don't really have any relation
between themselves.

周琰杰 (Zhou Yanjie) (5):
  MIPS: X1830: Respect cell count of common properties.
  dt-bindings: clock: Add documentation for MAC PHY control bindings.
  MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
  MIPS: CI20: Reduce clocksource to 750 kHz.
  MIPS: CI20: Add second percpu timer for SMP.

 .../devicetree/bindings/clock/ingenic,cgu.yaml     |  2 ++
 arch/mips/boot/dts/ingenic/ci20.dts                | 24 +++++++++++++---------
 arch/mips/boot/dts/ingenic/x1000.dtsi              |  7 +++++++
 arch/mips/boot/dts/ingenic/x1830.dtsi              | 16 ++++++++++-----
 4 files changed, 34 insertions(+), 15 deletions(-)

-- 
2.7.4

[PATCH v4 1/5] MIPS: X1830: Respect cell count of common properties.

[周琰杰 (Zhou Yanjie)]

If N fields of X cells should be provided, then that's what the
devicetree should represent, instead of having one single field of
(N * X) cells.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
---

Notes:
    v1->v2:
    No change.
    
    v2->v3:
    No change.
    
    v3->v4:
    No change.

 arch/mips/boot/dts/ingenic/x1830.dtsi | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index b21c930..59ca3a8 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -97,9 +97,9 @@
 
 		#clock-cells = <1>;
 
-		clocks = <&cgu X1830_CLK_RTCLK
-			  &cgu X1830_CLK_EXCLK
-			  &cgu X1830_CLK_PCLK>;
+		clocks = <&cgu X1830_CLK_RTCLK>,
+			 <&cgu X1830_CLK_EXCLK>,
+			 <&cgu X1830_CLK_PCLK>;
 		clock-names = "rtc", "ext", "pclk";
 
 		interrupt-controller;
@@ -274,8 +274,7 @@
 
 	pdma: dma-controller@13420000 {
 		compatible = "ingenic,x1830-dma";
-		reg = <0x13420000 0x400
-			   0x13421000 0x40>;
+		reg = <0x13420000 0x400>, <0x13421000 0x40>;
 		#dma-cells = <2>;
 
 		interrupt-parent = <&intc>;
-- 
2.7.4

[PATCH v4 2/5] dt-bindings: clock: Add documentation for MAC PHY control bindings.

[周琰杰 (Zhou Yanjie)]

Update the CGU binding documentation, add mac-phy-ctrl as a
pattern property.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
---

Notes:
    v3:
    New patch.
    
    v3->v4:
    No change.

 Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
index c65b945..ee9b5fb 100644
--- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
+++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
@@ -93,6 +93,8 @@ required:
 patternProperties:
   "^usb-phy@[a-f0-9]+$":
     allOf: [ $ref: "../phy/ingenic,phy-usb.yaml#" ]
+  "^mac-phy-ctrl@[a-f0-9]+$":
+    allOf: [ $ref: "../net/ingenic,mac.yaml#" ]
 
 additionalProperties: false
 
-- 
2.7.4

[PATCH v4 3/5] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.

[周琰杰 (Zhou Yanjie)]

Add MAC syscon nodes for X1000 SoC and X1830 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
---

Notes:
    v1->v2:
    No change.
    
    v2->v3:
    No change.
    
    v3->v4:
    No change.

 arch/mips/boot/dts/ingenic/x1000.dtsi | 7 +++++++
 arch/mips/boot/dts/ingenic/x1830.dtsi | 7 +++++++
 2 files changed, 14 insertions(+)

diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
index aac9ded..dec7909 100644
--- a/arch/mips/boot/dts/ingenic/x1000.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -80,6 +80,11 @@
 
 			status = "disabled";
 		};
+
+		mac_phy_ctrl: mac-phy-ctrl@e8 {
+			compatible = "syscon";
+			reg = <0xe8 0x4>;
+		};
 	};
 
 	ost: timer@12000000 {
@@ -347,6 +352,8 @@
 		clocks = <&cgu X1000_CLK_MAC>;
 		clock-names = "stmmaceth";
 
+		mode-reg = <&mac_phy_ctrl>;
+
 		status = "disabled";
 
 		mdio: mdio {
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index 59ca3a8..215257f 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -73,6 +73,11 @@
 
 			status = "disabled";
 		};
+
+		mac_phy_ctrl: mac-phy-ctrl@e8 {
+			compatible = "syscon";
+			reg = <0xe8 0x4>;
+		};
 	};
 
 	ost: timer@12000000 {
@@ -336,6 +341,8 @@
 		clocks = <&cgu X1830_CLK_MAC>;
 		clock-names = "stmmaceth";
 
+		mode-reg = <&mac_phy_ctrl>;
+
 		status = "disabled";
 
 		mdio: mdio {
-- 
2.7.4

[PATCH v4 4/5] MIPS: CI20: Reduce clocksource to 750 kHz.

[周琰杰 (Zhou Yanjie)]

The original clock (3 MHz) is too fast for the clocksource,
there will be a chance that the system may get stuck.

Reported-by: Nikolaus Schaller <hns@goldelico.com>
Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---

Notes:
    v4:
    New patch.

 arch/mips/boot/dts/ingenic/ci20.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 8877c62..3a4eaf1 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -525,10 +525,10 @@
 
 &tcu {
 	/*
-	 * 750 kHz for the system timer and 3 MHz for the clocksource,
+	 * 750 kHz for the system timer and clocksource,
 	 * use channel #0 for the system timer, #1 for the clocksource.
 	 */
 	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
 					  <&tcu TCU_CLK_OST>;
-	assigned-clock-rates = <750000>, <3000000>, <3000000>;
+	assigned-clock-rates = <750000>, <750000>, <3000000>;
 };
-- 
2.7.4

[PATCH v4 5/5] MIPS: CI20: Add second percpu timer for SMP.

[周琰杰 (Zhou Yanjie)]

1.Add a new TCU channel as the percpu timer of core1, this is to
  prepare for the subsequent SMP support. The newly added channel
  will not adversely affect the current single-core state.
2.Adjust the position of TCU node to make it consistent with the
  order in jz4780.dtsi file.

Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---

Notes:
    v2:
    New patch.
    
    v2->v3:
    No change.
    
    v3->v4:
    Improve TCU related notes.

 arch/mips/boot/dts/ingenic/ci20.dts | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 3a4eaf1..61c153b 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -118,6 +118,20 @@
 	assigned-clock-rates = <48000000>;
 };
 
+&tcu {
+	/*
+	 * 750 kHz for the system timers and clocksource,
+	 * use channel #0 and #1 for the per cpu system timers,
+	 * and use channel #2 for the clocksource.
+	 *
+	 * 3000 kHz for the OST timer to provide a higher
+	 * precision clocksource.
+	 */
+	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+					  <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
+	assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>;
+};
+
 &mmc0 {
 	status = "okay";
 
@@ -522,13 +536,3 @@
 		bias-disable;
 	};
 };
-
-&tcu {
-	/*
-	 * 750 kHz for the system timer and clocksource,
-	 * use channel #0 for the system timer, #1 for the clocksource.
-	 */
-	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
-					  <&tcu TCU_CLK_OST>;
-	assigned-clock-rates = <750000>, <750000>, <3000000>;
-};
-- 
2.7.4

Re: [PATCH v4 2/5] dt-bindings: clock: Add documentation for MAC PHY control bindings.

[Stephen Boyd]

Quoting 周琰杰 (Zhou Yanjie) (2021-06-25 23:18:38)
> Update the CGU binding documentation, add mac-phy-ctrl as a
> pattern property.
> 
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> Acked-by: Paul Cercueil <paul@crapouillou.net>
> ---

Acked-by: Stephen Boyd <sboyd@kernel.org>

Would also be good to add it to the example.

Re: [PATCH v4 2/5] dt-bindings: clock: Add documentation for MAC PHY control bindings.

[周琰杰]

Hi Stephen,

于 Sun, 27 Jun 2021 19:52:02 -0700
Stephen Boyd <sboyd@kernel.org> 写道:

> Quoting 周琰杰 (Zhou Yanjie) (2021-06-25 23:18:38)
> > Update the CGU binding documentation, add mac-phy-ctrl as a
> > pattern property.
> > 
> > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> > Acked-by: Paul Cercueil <paul@crapouillou.net>
> > ---  
> 
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> 

Thanks!

> Would also be good to add it to the example.

Unfortunately, mac-phy-ctrl only appeared after JZ4775 (include JZ4775),
but now the CGU driver of JZ4775 has not been merged into the mainline.
My plan is to wait for the CGU driver of JZ4775 to be merged into the
mainline and then add a new example based on JZ4775 :)

Thanks and best regards!

Re: [PATCH v4 4/5] MIPS: CI20: Reduce clocksource to 750 kHz.

[Paul Cercueil]

Hi Zhou,

Le sam., juin 26 2021 at 14:18:40 +0800, 周琰杰 (Zhou Yanjie) 
<zhouyanjie@wanyeetech.com> a écrit :
> The original clock (3 MHz) is too fast for the clocksource,
> there will be a chance that the system may get stuck.
> 
> Reported-by: Nikolaus Schaller <hns@goldelico.com>
> Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

Acked-by: Paul Cercueil <paul@crapouillou.net>

Cheers,
-Paul

> ---
> 
> Notes:
>     v4:
>     New patch.
> 
>  arch/mips/boot/dts/ingenic/ci20.dts | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts 
> b/arch/mips/boot/dts/ingenic/ci20.dts
> index 8877c62..3a4eaf1 100644
> --- a/arch/mips/boot/dts/ingenic/ci20.dts
> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
> @@ -525,10 +525,10 @@
> 
>  &tcu {
>  	/*
> -	 * 750 kHz for the system timer and 3 MHz for the clocksource,
> +	 * 750 kHz for the system timer and clocksource,
>  	 * use channel #0 for the system timer, #1 for the clocksource.
>  	 */
>  	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
>  					  <&tcu TCU_CLK_OST>;
> -	assigned-clock-rates = <750000>, <3000000>, <3000000>;
> +	assigned-clock-rates = <750000>, <750000>, <3000000>;
>  };
> --
> 2.7.4
> 

Re: [PATCH v4 5/5] MIPS: CI20: Add second percpu timer for SMP.

[Paul Cercueil]

Hi Zhou,

Le sam., juin 26 2021 at 14:18:41 +0800, 周琰杰 (Zhou Yanjie) 
<zhouyanjie@wanyeetech.com> a écrit :
> 1.Add a new TCU channel as the percpu timer of core1, this is to
>   prepare for the subsequent SMP support. The newly added channel
>   will not adversely affect the current single-core state.
> 2.Adjust the position of TCU node to make it consistent with the
>   order in jz4780.dtsi file.
> 
> Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

Again, you should avoid moving nodes like that.

Not sure it's worth asking for a v5, so:
Acked-by: Paul Cercueil <paul@crapouillou.net>

Cheers,
-Paul

> ---
> 
> Notes:
>     v2:
>     New patch.
> 
>     v2->v3:
>     No change.
> 
>     v3->v4:
>     Improve TCU related notes.
> 
>  arch/mips/boot/dts/ingenic/ci20.dts | 24 ++++++++++++++----------
>  1 file changed, 14 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts 
> b/arch/mips/boot/dts/ingenic/ci20.dts
> index 3a4eaf1..61c153b 100644
> --- a/arch/mips/boot/dts/ingenic/ci20.dts
> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
> @@ -118,6 +118,20 @@
>  	assigned-clock-rates = <48000000>;
>  };
> 
> +&tcu {
> +	/*
> +	 * 750 kHz for the system timers and clocksource,
> +	 * use channel #0 and #1 for the per cpu system timers,
> +	 * and use channel #2 for the clocksource.
> +	 *
> +	 * 3000 kHz for the OST timer to provide a higher
> +	 * precision clocksource.
> +	 */
> +	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
> +					  <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
> +	assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>;
> +};
> +
>  &mmc0 {
>  	status = "okay";
> 
> @@ -522,13 +536,3 @@
>  		bias-disable;
>  	};
>  };
> -
> -&tcu {
> -	/*
> -	 * 750 kHz for the system timer and clocksource,
> -	 * use channel #0 for the system timer, #1 for the clocksource.
> -	 */
> -	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
> -					  <&tcu TCU_CLK_OST>;
> -	assigned-clock-rates = <750000>, <750000>, <3000000>;
> -};
> --
> 2.7.4
> 

Re: [PATCH v4 0/5] Misc Ingenic patches.

[Thomas Bogendoerfer]

On Sat, Jun 26, 2021 at 02:18:36PM +0800, 周琰杰 (Zhou Yanjie) wrote:
> Some misc patches that don't really have any relation
> between themselves.
> 
> 周琰杰 (Zhou Yanjie) (5):
>   MIPS: X1830: Respect cell count of common properties.
>   dt-bindings: clock: Add documentation for MAC PHY control bindings.
>   MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
>   MIPS: CI20: Reduce clocksource to 750 kHz.
>   MIPS: CI20: Add second percpu timer for SMP.
> 
>  .../devicetree/bindings/clock/ingenic,cgu.yaml     |  2 ++
>  arch/mips/boot/dts/ingenic/ci20.dts                | 24 +++++++++++++---------
>  arch/mips/boot/dts/ingenic/x1000.dtsi              |  7 +++++++
>  arch/mips/boot/dts/ingenic/x1830.dtsi              | 16 ++++++++++-----
>  4 files changed, 34 insertions(+), 15 deletions(-)

applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH v4 5/5] MIPS: CI20: Add second percpu timer for SMP.

[Zhou Yanjie]

On 2021/6/30 下午8:24, Paul Cercueil wrote:
> Hi Zhou,
>
> Le sam., juin 26 2021 at 14:18:41 +0800, 周琰杰 (Zhou Yanjie) 
> <zhouyanjie@wanyeetech.com> a écrit :
>> 1.Add a new TCU channel as the percpu timer of core1, this is to
>>   prepare for the subsequent SMP support. The newly added channel
>>   will not adversely affect the current single-core state.
>> 2.Adjust the position of TCU node to make it consistent with the
>>   order in jz4780.dtsi file.
>>
>> Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20
>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>
> Again, you should avoid moving nodes like that.


Oops, sorry, forgot to fix it, I will be more careful next time.


>
> Not sure it's worth asking for a v5, so:
> Acked-by: Paul Cercueil <paul@crapouillou.net>
>

Thanks!


> Cheers,
> -Paul
>
>> ---
>>
>> Notes:
>>     v2:
>>     New patch.
>>
>>     v2->v3:
>>     No change.
>>
>>     v3->v4:
>>     Improve TCU related notes.
>>
>>  arch/mips/boot/dts/ingenic/ci20.dts | 24 ++++++++++++++----------
>>  1 file changed, 14 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts 
>> b/arch/mips/boot/dts/ingenic/ci20.dts
>> index 3a4eaf1..61c153b 100644
>> --- a/arch/mips/boot/dts/ingenic/ci20.dts
>> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
>> @@ -118,6 +118,20 @@
>>      assigned-clock-rates = <48000000>;
>>  };
>>
>> +&tcu {
>> +    /*
>> +     * 750 kHz for the system timers and clocksource,
>> +     * use channel #0 and #1 for the per cpu system timers,
>> +     * and use channel #2 for the clocksource.
>> +     *
>> +     * 3000 kHz for the OST timer to provide a higher
>> +     * precision clocksource.
>> +     */
>> +    assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
>> +                      <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
>> +    assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>;
>> +};
>> +
>>  &mmc0 {
>>      status = "okay";
>>
>> @@ -522,13 +536,3 @@
>>          bias-disable;
>>      };
>>  };
>> -
>> -&tcu {
>> -    /*
>> -     * 750 kHz for the system timer and clocksource,
>> -     * use channel #0 for the system timer, #1 for the clocksource.
>> -     */
>> -    assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
>> -                      <&tcu TCU_CLK_OST>;
>> -    assigned-clock-rates = <750000>, <750000>, <3000000>;
>> -};
>> -- 
>> 2.7.4
>>
>