From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: Stefan Riedmueller <s.riedmueller@phytec.de>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Rob Herring <robh+dt@kernel.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Subject: Re: [PATCH v3 1/6] media: mt9p031: Read back the real clock rate
Date: Mon, 5 Jul 2021 10:13:43 +0300 [thread overview]
Message-ID: <20210705071343.GR3@paasikivi.fi.intel.com> (raw)
In-Reply-To: <20210702095922.118614-2-s.riedmueller@phytec.de>
Hi Enrico,
On Fri, Jul 02, 2021 at 11:59:17AM +0200, Stefan Riedmueller wrote:
> From: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
>
> The real and requested clock can differ and because it is used to
> calculate PLL values, the real clock rate should be read.
Do you have a system where this happens? That suggests there's a wrong
value in DT.
The preference nowadays is to rely on assigned-clock-rates, even though
it's inherently somewhat unreliable, just as clk_set_rate(). This is an
existing driver though. The old ones could be kept for compatibility with
older DT binaries.
>
> Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/media/i2c/mt9p031.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c
> index 77567341ec98..3eaaa8d44523 100644
> --- a/drivers/media/i2c/mt9p031.c
> +++ b/drivers/media/i2c/mt9p031.c
> @@ -255,6 +255,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031)
>
> struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
> struct mt9p031_platform_data *pdata = mt9p031->pdata;
> + unsigned long ext_freq;
> int ret;
>
> mt9p031->clk = devm_clk_get(&client->dev, NULL);
> @@ -265,13 +266,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031)
> if (ret < 0)
> return ret;
>
> + ext_freq = clk_get_rate(mt9p031->clk);
> +
> /* If the external clock frequency is out of bounds for the PLL use the
> * pixel clock divider only and disable the PLL.
> */
> - if (pdata->ext_freq > limits.ext_clock_max) {
> + if (ext_freq > limits.ext_clock_max) {
> unsigned int div;
>
> - div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq);
> + div = DIV_ROUND_UP(ext_freq, pdata->target_freq);
> div = roundup_pow_of_two(div) / 2;
>
> mt9p031->clk_div = min_t(unsigned int, div, 64);
> @@ -280,7 +283,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031)
> return 0;
> }
>
> - mt9p031->pll.ext_clock = pdata->ext_freq;
> + mt9p031->pll.ext_clock = ext_freq;
> mt9p031->pll.pix_clock = pdata->target_freq;
> mt9p031->use_pll = true;
>
--
Kind regards,
Sakari Ailus
next prev parent reply other threads:[~2021-07-05 7:13 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-02 9:59 [PATCH v3 0/6] media: mt9p031: Read back the real clock rate Stefan Riedmueller
2021-07-02 9:59 ` [PATCH v3 1/6] " Stefan Riedmueller
2021-07-05 7:13 ` Sakari Ailus [this message]
2021-07-05 7:42 ` Stefan Riedmüller
2021-07-02 9:59 ` [PATCH v3 2/6] media: mt9p031: Make pixel clock polarity configurable by DT Stefan Riedmueller
2021-07-02 9:59 ` [PATCH v3 3/6] dt-bindings: media: mt9p031: Add missing required properties Stefan Riedmueller
2021-07-02 13:15 ` Laurent Pinchart
2021-07-05 15:00 ` Stefan Riedmüller
2021-07-02 9:59 ` [PATCH v3 4/6] dt-bindings: media: mt9p031: add pclk-sample property Stefan Riedmueller
2021-07-02 9:59 ` [PATCH v3 5/6] media: mt9p031: Fix corrupted frame after restarting stream Stefan Riedmueller
2021-07-02 9:59 ` [PATCH v3 6/6] media: mt9p031: Use BIT macro Stefan Riedmueller
2021-07-02 13:13 ` Laurent Pinchart
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