From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D939AC11F68 for ; Sat, 10 Jul 2021 01:33:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C759C613CC for ; Sat, 10 Jul 2021 01:33:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231642AbhGJBfr (ORCPT ); Fri, 9 Jul 2021 21:35:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231602AbhGJBfn (ORCPT ); Fri, 9 Jul 2021 21:35:43 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F9D9C0613E5 for ; Fri, 9 Jul 2021 18:32:58 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id x25so14073023lfu.13 for ; Fri, 09 Jul 2021 18:32:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5qhvMLleXU8XB+hP5k6t45pc4R6yiwCRVKRmnoSH9uY=; b=NC794FtPnTVb6jwGxk8olKK4GLQcUz8otGUoiN3jZj8/lRUyRjfrHf6PkBr7TpskOd k/DAfrexwr1d0Dic1t2+ZnlIrNdlNXeIsbL8gXN5LhqmjjjFl6BcZff4i3M0RPyMIfav 4OvdRffu4Xlm0X9MPd0ZxqDogJa5hocWCA1OpYqXIvBkqvsYG/hR6Vb3PueGnLZ0zb/C sJiWDkrsiDkop0si9JGdq+oNgDKK9kpQOvMlh7ccW+dtVZQ/kBFF7i8/7A4/+YbbNGEP LoAIOiISvf7fQGJ72WnkrP0TOnttwgei0paaHuYa5YN+ppqCUo9e4/mA1vo6FoueXI3n D/TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5qhvMLleXU8XB+hP5k6t45pc4R6yiwCRVKRmnoSH9uY=; b=Wovm56TcbORefQkCDzxOHaxim9joV91KDtewrS59wJvXIOET/cuShfw/FuzY33OD7w eAoAVYenEdFw1mVyWuPrz39l4VkNbmr5npdxcNObftUXixTvzq0Mi8MLr1tzQIdtCAbE 6xySNZhDo3XrGch3Oj7TjyTMuAs+Y5f2m29VMqfW2f8guEGLKOD/F57E7duJrKjViFfT OTkoPaN5Z6IF9TgAtJtxH80lKuVaWAWSyxiracKI4JJlWOodvFbm+qb4NuMbN445NkiK rccy4qx3crCu5Z54WczefctmS7+wOdl/yRR712EA9fNqA+PnLZG++kNxLJSOemBDe7gX OEPw== X-Gm-Message-State: AOAM533qQeOuPG1KQjWjPL+7eIYLa/CHWldelaK+N4nUDM8jrFK+chE4 fIyd28Xn8IFgXi61iIYcgq4MBQ== X-Google-Smtp-Source: ABdhPJz9jcG35w9SWS3uxRL6ARRlS5cpPeZv89o6TTwQw6/6CYd9Xtr7YTZmI8olO1MZX05tsjt0GQ== X-Received: by 2002:ac2:4259:: with SMTP id m25mr905215lfl.357.1625880776743; Fri, 09 Jul 2021 18:32:56 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p13sm588788lfh.206.2021.07.09.18.32.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 18:32:56 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v4 2/6] dt-bindings: clock: qcom,videocc: add mmcx power domain Date: Sat, 10 Jul 2021 04:32:49 +0300 Message-Id: <20210710013253.1134341-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210710013253.1134341-1-dmitry.baryshkov@linaro.org> References: <20210710013253.1134341-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 videocc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,videocc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 567202942b88..db4ada6acf27 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -47,6 +47,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -61,6 +66,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0x0ab00000 0x10000>; @@ -69,5 +75,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ... -- 2.30.2