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Mon, 12 Jul 2021 12:22:10 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.248]) by smtp.gmail.com with ESMTPSA id j24sm3350224ioo.16.2021.07.12.12.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jul 2021 12:22:10 -0700 (PDT) Received: (nullmailer pid 2333729 invoked by uid 1000); Mon, 12 Jul 2021 19:22:07 -0000 Date: Mon, 12 Jul 2021 13:22:07 -0600 From: Rob Herring To: Anup Patel Cc: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bin Meng Subject: Re: [RFC PATCH v2 06/11] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Message-ID: <20210712192207.GA2322460@robh.at.kernel.org> References: <20210618123851.1344518-1-anup.patel@wdc.com> <20210618123851.1344518-7-anup.patel@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210618123851.1344518-7-anup.patel@wdc.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Jun 18, 2021 at 06:08:46PM +0530, Anup Patel wrote: > We add DT bindings documentation for the ACLINT MSWI and SSWI > devices found on RISC-V SOCs. > > Signed-off-by: Anup Patel > Reviewed-by: Bin Meng > --- > .../riscv,aclint-swi.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > new file mode 100644 > index 000000000000..b74025542866 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V ACLINT Software Interrupt Devices > + > +maintainers: > + - Anup Patel > + > +description: > + RISC-V SOCs include an implementation of the M-level software interrupt > + (MSWI) device and the S-level software interrupt (SSWI) device defined > + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. > + > + The ACLINT MSWI and SSWI devices are documented in the RISC-V ACLINT > + specification located at > + https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc. > + > + The ACLINT MSWI and SSWI devices directly connect to the M-level and > + S-level software interrupt lines of various HARTs (or CPUs) respectively > + so the RISC-V per-HART (or per-CPU) local interrupt controller is the > + parent interrupt controller for the ACLINT MSWI and SSWI devices. > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - riscv,aclint-mswi > + - riscv,aclint-sswi > + > + description: > + Should be ",-aclint-mswi" and "riscv,aclint-mswi" OR > + ",-aclint-sswi" and "riscv,aclint-sswi". The schema doesn't match the description. There's no actual vendor implementation yet? You could do: items: - {} - const: riscv,aclint-mswi But then your example will fail. > + > + reg: > + maxItems: 1 > + > + "#interrupt-cells": > + const: 0 > + > + interrupts-extended: > + minItems: 1 You need maxItems too. I guess this based on number of cores, so just pick a 'should be enough' value. > + > + interrupt-controller: true > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts-extended > + - interrupt-controller > + - "#interrupt-cells" > + > +examples: > + - | > + // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel): > + > + interrupt-controller@2000000 { > + compatible = "riscv,aclint-mswi"; > + interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>; interrupts-extended = <&cpu1intc 3>, <&cpu2intc 3>, <&cpu3intc 3>, <&cpu4intc 3>; > + reg = <0x2000000 0x4000>; > + interrupt-controller; > + #interrupt-cells = <0>; > + }; > + > + - | > + // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel): > + > + interrupt-controller@2100000 { > + compatible = "riscv,aclint-sswi"; > + interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>; Same here. > + reg = <0x2100000 0x4000>; > + interrupt-controller; > + #interrupt-cells = <0>; > + }; > +... > -- > 2.25.1 > >