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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id j7sm1854952pjf.41.2021.11.30.01.17.12 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 30 Nov 2021 01:17:14 -0800 (PST) Date: Tue, 30 Nov 2021 17:17:08 +0800 From: Shawn Guo To: Marc Zyngier Cc: Thomas Gleixner , Maulik Shah , Bjorn Andersson , Rob Herring , Loic Poulain , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/2] irqchip: Add Qualcomm MPM controller driver Message-ID: <20211130091708.GH10105@dragon> References: <20211126093529.31661-1-shawn.guo@linaro.org> <20211126093529.31661-3-shawn.guo@linaro.org> <87czmmbu8k.wl-maz@kernel.org> <20211129133308.GB10105@dragon> <87pmqjm1c8.wl-maz@kernel.org> <20211130023151.GD10105@dragon> <87lf16m3ua.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87lf16m3ua.wl-maz@kernel.org> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Nov 30, 2021 at 08:42:53AM +0000, Marc Zyngier wrote: > On Tue, 30 Nov 2021 02:31:52 +0000, > Shawn Guo wrote: > > > > + Maulik > > > > On Mon, Nov 29, 2021 at 03:24:39PM +0000, Marc Zyngier wrote: > > [...] > > > > > > @@ -430,6 +430,14 @@ config QCOM_PDC > > > > > > Power Domain Controller driver to manage and configure wakeup > > > > > > IRQs for Qualcomm Technologies Inc (QTI) mobile chips. > > > > > > > > > > > > +config QCOM_MPM > > > > > > + bool "QCOM MPM" > > > > > > > > > > Can't be built as a module? > > > > > > > > The driver is implemented as a builtin_platform_driver(). > > > > > > This, on its own, shouldn't preclude the driver from being built as a > > > module. However, the config option only allows it to be built in. Why? > > > > I just tried to build it as a module, and it seems that "irq_to_desc" is > > only available for built-in build. > > Yet another thing that you should not be using. The irqdomain code > gives you everything you need without having to resort to the > internals of the core IRQ infrastructure. I see. I should use irq_get_irq_data() rather than &desc->irq_data. > > > > Furthermore, why would you look up anywhere other than the wake-up > > > domain? My impression was that only these interrupts would require > > > being re-triggered. > > > > Both domains have MPM pins that could wake up system. > > Then why do you need two domains? This is basically the same situation as qcom-pdc, and I have some description about that in the commit log: - For given SoC, a fixed number of MPM pins are supported, e.g. 96 pins on QCM2290. Each of these MPM pins can be either a MPM_GIC pin or a MPM_GPIO pin. The mapping between MPM_GIC pin and GIC interrupt is defined by SoC, as well as the mapping between MPM_GPIO pin and GPIO number. The former mapping can be found as the SoC data in this MPM driver, while the latter can be found as the msm_gpio_wakeirq_map[] in TLMM driver. - Two irq domains are created for a single irq_chip to handle MPM_GIC and MPM_GPIO pins respectively, i.e. MPM_GIC domain and MPM_GPIO domain. The former is a child domain of GIC irq domain, while the latter is a parent domain of TLMM/GPIO irq domain. Shawn