From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BA2CC433EF for ; Wed, 12 Jan 2022 16:34:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349848AbiALQew (ORCPT ); Wed, 12 Jan 2022 11:34:52 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:38038 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1355291AbiALQel (ORCPT ); Wed, 12 Jan 2022 11:34:41 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20CAjf5I018214; Wed, 12 Jan 2022 17:34:25 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=tsZZYByhBt3iMrVmHEOmuez8eGtVX2YnJRTRXajIhto=; b=23JDogZfQLRE+QI9XfydsgVWdlqKnI39iHWp0SDb2i7E+RITFfZ6w30kwnJm4HnnLJrp /w2PPtPq4s+V/1/MLOZv3gaCojb1+OWTL82FlSAYjOERHIEit6oOBMehbrxySU4bH7DZ bMEjVGpcQr6ISvoJuZpoYNf3qgUsDVeSWcRlp0bfQ6DGDrzplExQwCMBKEW9i19+9rTw VsAJlpCTvI0n0u+fI1bCi4whVYYItWaOe7TeebCQkyr3c25RICPK+zZIC72jHEZAu9Qa Kjp0sQVzA8Pyn4ozljZvB6DYkEKntrPRuqzfioCxpMJY0Srn9/a+YVLt6V8S3rJ1hVK/ sw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3dhssdugv6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Jan 2022 17:34:25 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7A0A410002A; Wed, 12 Jan 2022 17:34:24 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 718E424B8BB; Wed, 12 Jan 2022 17:34:24 +0100 (CET) Received: from localhost (10.75.127.48) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 12 Jan 2022 17:34:24 +0100 From: Yann Gautier To: Rob Herring , Alexandre Torgue , Maxime Coquelin , , , CC: , , Yann Gautier Subject: [PATCH 10/10] ARM: dts: stm32: add sdmmc2 pins for STM32MP13 Date: Wed, 12 Jan 2022 17:33:56 +0100 Message-ID: <20220112163356.25634-11-yann.gautier@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220112163356.25634-9-yann.gautier@foss.st.com> References: <20220112163356.25634-9-yann.gautier@foss.st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-12_04,2022-01-11_01,2021-12-02_01 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Those pins are used for SDIO on STM32MP135F-DK board. Signed-off-by: Yann Gautier --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 51 ++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index c6f78eef3698..d2472cd8f1d0 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -57,6 +57,57 @@ }; }; + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + sdmmc2_clk_pins_a: sdmmc2-clk-0 { + pins { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ -- 2.17.1