From: Bhadram Varka <vbhadram@nvidia.com>
To: <netdev@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>
Cc: <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kuba@kernel.org>, <catalin.marinas@arm.com>, <will@kernel.org>,
Thierry Reding <treding@nvidia.com>,
Bhadram Varka <vbhadram@nvidia.com>
Subject: [PATCH net-next v1 6/9] arm64: tegra: Add MGBE nodes on Tegra234
Date: Thu, 23 Jun 2022 13:16:12 +0530 [thread overview]
Message-ID: <20220623074615.56418-6-vbhadram@nvidia.com> (raw)
In-Reply-To: <20220623074615.56418-1-vbhadram@nvidia.com>
From: Thierry Reding <treding@nvidia.com>
Add MGBE IP DT nodes in SOC DT files.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 136 +++++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index cb3af539e477..b77b55e80223 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -791,6 +791,142 @@
#mbox-cells = <2>;
};
+ ethernet@6800000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06800000 0x10000>,
+ <0x06810000 0x10000>,
+ <0x068a0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX>,
+ <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE0_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
+ status = "disabled";
+ };
+
+ ethernet@6900000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06900000 0x10000>,
+ <0x06910000 0x10000>,
+ <0x069a0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
+ <&bpmp TEGRA234_CLK_MGBE1_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE1_TX>,
+ <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE1_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
+ status = "disabled";
+ };
+
+ ethernet@6a00000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06a00000 0x10000>,
+ <0x06a10000 0x10000>,
+ <0x06aa0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
+ <&bpmp TEGRA234_CLK_MGBE2_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE2_TX>,
+ <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE2_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
+ status = "disabled";
+ };
+
+ ethernet@6b00000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06b00000 0x10000>,
+ <0x06b10000 0x10000>,
+ <0x06ba0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
+ <&bpmp TEGRA234_CLK_MGBE3_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE3_TX>,
+ <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE3_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
+ status = "disabled";
+ };
+
smmu_niso1: iommu@8000000 {
compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
reg = <0x8000000 0x1000000>,
--
2.17.1
next prev parent reply other threads:[~2022-06-23 7:47 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-23 7:46 [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Bhadram Varka
2022-06-23 7:46 ` [PATCH net-next v1 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets Bhadram Varka
2022-06-24 16:02 ` Krzysztof Kozlowski
2022-06-24 16:21 ` Thierry Reding
2022-06-24 17:12 ` Krzysztof Kozlowski
2022-06-23 7:46 ` [PATCH net-next v1 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients Bhadram Varka
2022-06-24 16:06 ` (subset) " Krzysztof Kozlowski
2022-06-24 16:10 ` Krzysztof Kozlowski
2022-06-24 16:19 ` Thierry Reding
2022-06-25 20:18 ` Krzysztof Kozlowski
2022-06-23 7:46 ` [PATCH net-next v1 4/9] memory: tegra: Add MGBE memory clients for Tegra234 Bhadram Varka
2022-06-24 16:06 ` (subset) " Krzysztof Kozlowski
2022-06-24 16:24 ` Thierry Reding
2022-06-25 20:17 ` Krzysztof Kozlowski
2022-06-25 20:18 ` Krzysztof Kozlowski
2022-06-23 7:46 ` [PATCH net-next v1 5/9] dt-bindings: net: Add Tegra234 MGBE Bhadram Varka
2022-06-28 19:55 ` Rob Herring
2022-06-30 14:54 ` Thierry Reding
2022-07-07 4:10 ` Bhadram Varka
2022-06-23 7:46 ` Bhadram Varka [this message]
2022-06-23 7:46 ` [PATCH net-next v1 7/9] arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit Bhadram Varka
2022-06-23 7:46 ` [PATCH net-next v1 8/9] stmmac: tegra: Add MGBE support Bhadram Varka
2022-06-24 18:16 ` Jakub Kicinski
2022-06-23 7:46 ` [PATCH net-next v1 9/9] arm64: defconfig: Enable Tegra MGBE driver Bhadram Varka
2022-06-24 16:02 ` [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Krzysztof Kozlowski
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