From: Conor Dooley <conor.dooley@microchip.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
"David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Conor Dooley <conor.dooley@microchip.com>,
"Nicolas Ferre" <nicolas.ferre@microchip.com>,
Claudiu Beznea <claudiu.beznea@microchip.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
"Daire McNamara" <daire.mcnamara@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<netdev@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: [PATCH v1 06/14] net: macb: add polarfire soc reset support
Date: Thu, 30 Jun 2022 09:05:25 +0100 [thread overview]
Message-ID: <20220630080532.323731-7-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220630080532.323731-1-conor.dooley@microchip.com>
To date, the Microchip PolarFire SoC (MPFS) has been using the
cdns,macb compatible, however the generic device does not have reset
support. Add a new compatible & .data for MPFS to hook into the reset
functionality added for zynqmp support (and make the zynqmp init
function generic in the process).
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/net/ethernet/cadence/macb_main.c | 25 +++++++++++++++++-------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index d89098f4ede8..325f0463fd42 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -4689,33 +4689,32 @@ static const struct macb_config np4_config = {
.usrio = &macb_default_usrio,
};
-static int zynqmp_init(struct platform_device *pdev)
+static int init_reset_optional(struct platform_device *pdev)
{
struct net_device *dev = platform_get_drvdata(pdev);
struct macb *bp = netdev_priv(dev);
int ret;
if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
- /* Ensure PS-GTR PHY device used in SGMII mode is ready */
+ /* Ensure PHY device used in SGMII mode is ready */
bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL);
if (IS_ERR(bp->sgmii_phy)) {
ret = PTR_ERR(bp->sgmii_phy);
dev_err_probe(&pdev->dev, ret,
- "failed to get PS-GTR PHY\n");
+ "failed to get SGMII PHY\n");
return ret;
}
ret = phy_init(bp->sgmii_phy);
if (ret) {
- dev_err(&pdev->dev, "failed to init PS-GTR PHY: %d\n",
+ dev_err(&pdev->dev, "failed to init SGMII PHY: %d\n",
ret);
return ret;
}
}
- /* Fully reset GEM controller at hardware level using zynqmp-reset driver,
- * if mapped in device tree.
+ /* Fully reset controller at hardware level if mapped in device tree
*/
ret = device_reset_optional(&pdev->dev);
if (ret) {
@@ -4737,7 +4736,7 @@ static const struct macb_config zynqmp_config = {
MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
.dma_burst_length = 16,
.clk_init = macb_clk_init,
- .init = zynqmp_init,
+ .init = init_reset_optional,
.jumbo_max_len = 10240,
.usrio = &macb_default_usrio,
};
@@ -4751,6 +4750,17 @@ static const struct macb_config zynq_config = {
.usrio = &macb_default_usrio,
};
+static const struct macb_config mpfs_config = {
+ .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
+ MACB_CAPS_JUMBO |
+ MACB_CAPS_GEM_HAS_PTP,
+ .dma_burst_length = 16,
+ .clk_init = macb_clk_init,
+ .init = init_reset_optional,
+ .usrio = &macb_default_usrio,
+ .jumbo_max_len = 10240,
+};
+
static const struct macb_config sama7g5_gem_config = {
.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
MACB_CAPS_MIIONRGMII,
@@ -4787,6 +4797,7 @@ static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
{ .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
+ { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
{ .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
{ .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
{ /* sentinel */ }
--
2.36.1
next prev parent reply other threads:[~2022-06-30 8:08 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-30 8:05 [PATCH v1 00/14] PolarFire SoC reset controller & clock cleanups Conor Dooley
2022-06-30 8:05 ` [PATCH v1 01/14] dt-bindings: clk: microchip: mpfs: add reset controller support Conor Dooley
2022-07-01 19:51 ` Rob Herring
2022-06-30 8:05 ` [PATCH v1 02/14] dt-bindings: net: cdns,macb: document polarfire soc's macb Conor Dooley
2022-06-30 8:05 ` [PATCH v1 03/14] clk: microchip: mpfs: add reset controller Conor Dooley
2022-06-30 8:05 ` [PATCH v1 04/14] reset: add polarfire soc reset support Conor Dooley
2022-06-30 9:12 ` Philipp Zabel
2022-06-30 16:20 ` Conor.Dooley
2022-07-01 16:20 ` Conor.Dooley
2022-06-30 8:05 ` [PATCH v1 05/14] MAINTAINERS: add polarfire soc reset controller Conor Dooley
2022-06-30 8:05 ` Conor Dooley [this message]
2022-06-30 16:02 ` [PATCH v1 06/14] net: macb: add polarfire soc reset support Jakub Kicinski
2022-06-30 16:14 ` Conor.Dooley
2022-06-30 8:05 ` [PATCH v1 07/14] riscv: dts: microchip: add mpfs specific macb " Conor Dooley
2022-06-30 8:05 ` [PATCH v1 08/14] clk: microchip: mpfs: add module_authors entries Conor Dooley
2022-06-30 8:05 ` [PATCH v1 09/14] clk: microchip: mpfs: add MSS pll's set & round rate Conor Dooley
2022-06-30 8:05 ` [PATCH v1 10/14] clk: microchip: mpfs: move id & offset out of clock structs Conor Dooley
2022-06-30 8:05 ` [PATCH v1 11/14] clk: microchip: mpfs: simplify control reg access Conor Dooley
2022-06-30 8:05 ` [PATCH v1 12/14] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() Conor Dooley
2022-06-30 8:05 ` [PATCH v1 13/14] clk: microchip: mpfs: convert cfg_clk to clk_divider Conor Dooley
2022-07-02 14:50 ` Conor.Dooley
2022-06-30 8:05 ` [PATCH v1 14/14] clk: microchip: mpfs: convert periph_clk to clk_gate Conor Dooley
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