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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id mp10-20020a17090b190a00b001f333fab3d6sm5817972pjb.18.2022.08.28.23.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Aug 2022 23:22:11 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache Date: Mon, 29 Aug 2022 06:22:00 +0000 Message-Id: <20220829062202.3287-2-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220829062202.3287-1-zong.li@sifive.com> References: <20220829062202.3287-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since composible cache may be L3 cache if private L2 cache exists, it should use its original name composible cache to prevent confusion. Signed-off-by: Greentime Hu Signed-off-by: Zong Li --- .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml similarity index 92% rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml index 69cdab18d629..1a64a5384e36 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml @@ -12,8 +12,8 @@ maintainers: - Paul Walmsley description: - The SiFive Level 2 Cache Controller is used to provide access to fast copies - of memory for masters in a Core Complex. The Level 2 Cache Controller also + The SiFive Composable Cache Controller is used to provide access to fast copies + of memory for masters in a Core Complex. The Composable Cache Controller also acts as directory-based coherency manager. All the properties in ePAPR/DeviceTree specification applies for this platform. @@ -27,6 +27,7 @@ select: enum: - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - sifive,ccache0 required: - compatible @@ -37,6 +38,7 @@ properties: - enum: - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - sifive,ccache0 - const: cache cache-block-size: -- 2.17.1