Re: [PATCH v2 13/16] dt-bindings: pinctrl: qcom,sm8250: fix matching pin config

[Bjorn Andersson <andersson@kernel.org>]

On Fri, Sep 30, 2022 at 09:29:51PM +0200, Krzysztof Kozlowski wrote:
> The TLMM pin controller follows generic pin-controller bindings, so
> should have subnodes with '-state' and '-pins'.  Otherwise the subnodes
> (level one and two) are not properly matched.  This method also unifies
> the bindings with other Qualcomm TLMM and LPASS pinctrl bindings.
> 
> The change causes indentation decrement, so the diff-hunk looks big, but
> there are no functional changes in the subnode "properties" section.
> The only difference there is removal of blank lines between common GPIO
> pinconf properties.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Reviewed-by: Bjorn Andersson <andersson@kernel.org>

> ---
>  .../bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 128 +++++++++---------
>  1 file changed, 67 insertions(+), 61 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
> index 021592b32904..131eb8c981f8 100644
> --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
> @@ -58,68 +58,74 @@ properties:
>  
>    wakeup-parent: true
>  
> -#PIN CONFIGURATION NODES
>  patternProperties:
> -  '^.*$':
> -    if:
> -      type: object
> -    then:
> -      $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
> -      properties:
> -        pins:
> -          description:
> -            List of gpio pins affected by the properties specified in this
> -            subnode.
> -          items:
> -            oneOf:
> -              - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
> -              - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
> -          minItems: 1
> -          maxItems: 36
> -
> -        function:
> -          description:
> -            Specify the alternative function to be configured for the specified
> -            pins.
> -
> -          enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
> -                  cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
> -                  cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
> -                  ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
> -                  ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
> -                  mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
> -                  mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
> -                  mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
> -                  pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
> -                  pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
> -                  qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
> -                  qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
> -                  qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
> -                  sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
> -                  tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
> -                  tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
> -                  tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
> -
> -        drive-strength:
> -          enum: [2, 4, 6, 8, 10, 12, 14, 16]
> -          default: 2
> -          description:
> -            Selects the drive strength for the specified pins, in mA.
> -
> -        bias-pull-down: true
> -
> -        bias-pull-up: true
> -
> -        bias-disable: true
> -
> -        output-high: true
> -
> -        output-low: true
> -
> -      required:
> -        - pins
> -
> -      additionalProperties: false
> +  "-state$":
> +    oneOf:
> +      - $ref: "#/$defs/qcom-sm8250-tlmm-state"
> +      - patternProperties:
> +          "-pins$":
> +            $ref: "#/$defs/qcom-sm8250-tlmm-state"
> +        additionalProperties: false
> +
> +$defs:
> +  qcom-sm8250-tlmm-state:
> +    type: object
> +    description:
> +      Pinctrl node's client devices use subnodes for desired pin configuration.
> +      Client device subnodes use below standard properties.
> +    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
> +
> +    properties:
> +      pins:
> +        description:
> +          List of gpio pins affected by the properties specified in this
> +          subnode.
> +        items:
> +          oneOf:
> +            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
> +            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
> +        minItems: 1
> +        maxItems: 36
> +
> +      function:
> +        description:
> +          Specify the alternative function to be configured for the specified
> +          pins.
> +
> +        enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
> +                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
> +                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
> +                ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
> +                ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
> +                mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
> +                mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
> +                mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
> +                pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
> +                pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
> +                qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
> +                qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
> +                qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
> +                sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
> +                tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
> +                tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
> +                tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
> +
> +      drive-strength:
> +        enum: [2, 4, 6, 8, 10, 12, 14, 16]
> +        default: 2
> +        description:
> +          Selects the drive strength for the specified pins, in mA.
> +
> +      bias-pull-down: true
> +      bias-pull-up: true
> +      bias-disable: true
> +      output-high: true
> +      output-low: true
> +
> +    required:
> +      - pins
> +
> +    additionalProperties: false
>  
>  allOf:
>    - $ref: "pinctrl.yaml#"
> -- 
> 2.34.1
>