From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Akhil P Oommen <quic_akhilpo@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Rob Clark <robdclark@chromium.org>,
Marijn Suijten <marijn.suijten@somainline.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: [PATCH v4 02/14] dt-bindings: display/msm/gmu: Add GMU wrapper
Date: Tue, 14 Mar 2023 16:28:33 +0100 [thread overview]
Message-ID: <20230223-topic-gmuwrapper-v4-2-e987eb79d03f@linaro.org> (raw)
In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org>
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat these de-facto GMU-less parts in a way that's very similar to their
GMU-equipped cousins, massively saving up on code duplication.
The "wrapper" register space was specifically designed to mimic the layout
of a real GMU, though it rather obviously does not have the M3 core et al.
To sum it all up, the GMU wrapper is essentially a register space within
the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks,
interrupts, multiple reg spaces, iommus and OPP. Document it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../devicetree/bindings/display/msm/gmu.yaml | 49 ++++++++++++++++------
1 file changed, 37 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index ab14e81cb050..021373e686e1 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -19,16 +19,18 @@ description: |
properties:
compatible:
- items:
- - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
- - const: qcom,adreno-gmu
+ oneOf:
+ - items:
+ - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
+ - const: qcom,adreno-gmu
+ - const: qcom,adreno-gmu-wrapper
reg:
- minItems: 3
+ minItems: 1
maxItems: 4
reg-names:
- minItems: 3
+ minItems: 1
maxItems: 4
clocks:
@@ -44,7 +46,6 @@ properties:
- description: GMU HFI interrupt
- description: GMU interrupt
-
interrupt-names:
items:
- const: hfi
@@ -72,14 +73,8 @@ required:
- compatible
- reg
- reg-names
- - clocks
- - clock-names
- - interrupts
- - interrupt-names
- power-domains
- power-domain-names
- - iommus
- - operating-points-v2
additionalProperties: false
@@ -216,6 +211,27 @@ allOf:
- const: cxo
- const: axi
- const: memnoc
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,adreno-gmu-wrapper
+ then:
+ properties:
+ reg:
+ items:
+ - description: GMU wrapper register space
+ reg-names:
+ items:
+ - const: gmu
+ else:
+ required:
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - iommus
+ - operating-points-v2
examples:
- |
@@ -249,3 +265,12 @@ examples:
iommus = <&adreno_smmu 5>;
operating-points-v2 = <&gmu_opp_table>;
};
+
+ gmu_wrapper: gmu@596a000 {
+ compatible = "qcom,adreno-gmu-wrapper";
+ reg = <0x0596a000 0x30000>;
+ reg-names = "gmu";
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx", "gx";
+ };
--
2.39.2
next prev parent reply other threads:[~2023-03-14 15:28 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-14 15:28 [PATCH v4 00/14] GMU-less A6xx support (A610, A619_holi) Konrad Dybcio
2023-03-14 15:28 ` [PATCH v4 01/14] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx Konrad Dybcio
2023-03-16 6:59 ` Krzysztof Kozlowski
2023-03-14 15:28 ` Konrad Dybcio [this message]
2023-03-16 7:09 ` [PATCH v4 02/14] dt-bindings: display/msm/gmu: Add GMU wrapper Krzysztof Kozlowski
2023-03-14 15:28 ` [PATCH v4 03/14] drm/msm/a6xx: Remove static keyword from sptprac en/disable functions Konrad Dybcio
2023-03-14 15:28 ` [PATCH v4 04/14] drm/msm/a6xx: Extend and explain UBWC config Konrad Dybcio
2023-03-25 18:33 ` Rob Clark
2023-03-14 15:28 ` [PATCH v4 05/14] drm/msm/a6xx: Introduce GMU wrapper support Konrad Dybcio
2023-03-14 15:28 ` [PATCH v4 06/14] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init Konrad Dybcio
2023-03-28 15:35 ` Dmitry Baryshkov
2023-03-14 15:28 ` [PATCH v4 07/14] drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations Konrad Dybcio
2023-03-14 15:28 ` [PATCH v4 08/14] drm/msm/a6xx: Add support for A619_holi Konrad Dybcio
2023-03-14 15:28 ` [PATCH v4 09/14] drm/msm/a6xx: Add A610 support Konrad Dybcio
2023-03-14 15:28 ` [PATCH v4 10/14] drm/msm/a6xx: Fix some A619 tunables Konrad Dybcio
2023-03-14 15:28 ` [PATCH v4 11/14] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching Konrad Dybcio
2023-03-14 15:28 ` [PATCH v4 12/14] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching Konrad Dybcio
2023-03-28 15:30 ` Dmitry Baryshkov
2023-03-14 15:28 ` [PATCH v4 13/14] drm/msm/a6xx: Add A619_holi speedbin support Konrad Dybcio
2023-03-28 15:31 ` Dmitry Baryshkov
2023-03-14 15:28 ` [PATCH v4 14/14] drm/msm/a6xx: Add A610 " Konrad Dybcio
2023-03-28 15:32 ` Dmitry Baryshkov
2023-03-29 1:12 ` [PATCH v4 00/14] GMU-less A6xx support (A610, A619_holi) Konrad Dybcio
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