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[79.139.233.37]) by smtp.googlemail.com with ESMTPSA id z5sm8268779lji.32.2019.12.07.08.00.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 07 Dec 2019 08:00:06 -0800 (PST) Subject: Re: [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver From: Dmitry Osipenko To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, mperttunen@nvidia.com, gregkh@linuxfoundation.org, sboyd@kernel.org, tglx@linutronix.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: allison@lohutok.net, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, mturquette@baylibre.com, horms+renesas@verge.net.au, Jisheng.Zhang@synaptics.com, krzk@kernel.org, arnd@arndb.de, spujar@nvidia.com, josephl@nvidia.com, vidyas@nvidia.com, daniel.lezcano@linaro.org, mmaddireddy@nvidia.com, markz@nvidia.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alexios.zavras@intel.com, alsa-devel@alsa-project.org References: <1575600535-26877-1-git-send-email-skomatineni@nvidia.com> <1575600535-26877-4-git-send-email-skomatineni@nvidia.com> <7cf4ff77-2f33-4ee5-0e09-5aa6aef3e8be@gmail.com> Message-ID: <288a1701-def6-d628-26bc-a305f817bdb1@gmail.com> Date: Sat, 7 Dec 2019 19:00:04 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 07.12.2019 18:53, Dmitry Osipenko пишет: > 07.12.2019 18:47, Dmitry Osipenko пишет: >> 07.12.2019 17:28, Dmitry Osipenko пишет: >>> 06.12.2019 05:48, Sowjanya Komatineni пишет: >>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 with >>>> mux and gate for each of these clocks. >>>> >>>> Currently these PMC clocks are registered by Tegra clock driver using >>>> clk_register_mux and clk_register_gate by passing PMC base address >>>> and register offsets and PMC programming for these clocks happens >>>> through direct PMC access by the clock driver. >>>> >>>> With this, when PMC is in secure mode any direct PMC access from the >>>> non-secure world does not go through and these clocks will not be >>>> functional. >>>> >>>> This patch adds these clocks registration with PMC as a clock provider >>>> for these clocks. clk_ops callback implementations for these clocks >>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC programming >>>> in secure mode and non-secure mode. >>>> >>>> Signed-off-by: Sowjanya Komatineni >>>> --- >> >> [snip] >> >>>> + >>>> +static const struct clk_ops pmc_clk_gate_ops = { >>>> + .is_enabled = pmc_clk_is_enabled, >>>> + .enable = pmc_clk_enable, >>>> + .disable = pmc_clk_disable, >>>> +}; >>> >>> What's the benefit of separating GATE from the MUX? >>> >>> I think it could be a single clock. >> >> According to TRM: >> >> 1. GATE and MUX are separate entities. >> >> 2. GATE is the parent of MUX (see PMC's CLK_OUT paths diagram in TRM). >> >> 3. PMC doesn't gate EXTPERIPH clock but could "force-enable" it, correct? > > 4. clk_m_div2/4 are internal PMC OSC dividers and thus these clocks > should belong to PMC. Also, it should be "osc" and not "clk_m".