From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D834C43334 for ; Fri, 10 Jun 2022 02:11:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242627AbiFJCLE (ORCPT ); Thu, 9 Jun 2022 22:11:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232921AbiFJCLD (ORCPT ); Thu, 9 Jun 2022 22:11:03 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5800C32A8C5; Thu, 9 Jun 2022 19:11:01 -0700 (PDT) X-UUID: 813aaf29de8243c1bdc57ca68999bb53-20220610 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:9e4ab65c-012e-47d0-9701-33942f9fedcb,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:45 X-CID-INFO: VERSION:1.1.5,REQID:9e4ab65c-012e-47d0-9701-33942f9fedcb,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTIO N:release,TS:45 X-CID-META: VersionHash:2a19b09,CLOUDID:34eb52e5-2ba2-4dc1-b6c5-11feb6c769e0,C OID:01099fb91726,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 813aaf29de8243c1bdc57ca68999bb53-20220610 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 721379247; Fri, 10 Jun 2022 10:10:55 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 10 Jun 2022 10:10:54 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 10 Jun 2022 10:10:48 +0800 Message-ID: <3ced724e0067e105c11889a5d1bf3247ed57e520.camel@mediatek.com> Subject: Re: [PATCH v10 18/21] drm/mediatek: Add mt8195 Embedded DisplayPort driver From: Rex-BC Chen To: CK Hu , Guillaume Ranquet , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun =?UTF-8?Q?=28=E4=BA=91=E6=98=A5=E5=B3=B0=29?= , Kishon Vijay Abraham I , Vinod Koul , "Helge Deller" , Jitao Shi =?UTF-8?Q?=28=E7=9F=B3=E8=AE=B0=E6=B6=9B=29?= CC: Markus Schneider-Pargmann , "dri-devel@lists.freedesktop.org" , "linux-mediatek@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-phy@lists.infradead.org" , "linux-fbdev@vger.kernel.org" Date: Fri, 10 Jun 2022 10:10:40 +0800 In-Reply-To: References: <20220523104758.29531-1-granquet@baylibre.com> <20220523104758.29531-19-granquet@baylibre.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 2022-06-09 at 17:37 +0800, CK Hu wrote: > Hi, Rex: > > On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote: > > From: Markus Schneider-Pargmann > > > > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC. > > > > It supports the mt8195, the embedded DisplayPort units. It offers > > DisplayPort 1.4 with up to 4 lanes. > > > > The driver creates a child device for the phy. The child device > > will > > never exist without the parent being active. As they are sharing a > > register range, the parent passes a regmap pointer to the child so > > that > > both can work with the same register range. The phy driver sets > > device > > data that is read by the parent to get the phy device that can be > > used > > to control the phy properties. > > > > This driver is based on an initial version by > > Jason-JH.Lin . > > > > Signed-off-by: Markus Schneider-Pargmann > > Signed-off-by: Guillaume Ranquet > > --- > > [snip] > > > + > > +static int mtk_dp_power_disable(struct mtk_dp *mtk_dp) > > +{ > > + int ret; > > + > > + ret = mtk_dp_write(mtk_dp, MTK_DP_TOP_PWR_STATE, 0); > > + > > + if (ret) > > + return ret; > > + > > + ret = mtk_dp_write(mtk_dp, MTK_DP_0034, > > MTK_DP_0034 is defined as: > > +#define MTK_DP_0034 (BIT(2) | BIT(4) | BIT(5)) > > I think this a weird address. > > > + DA_CKM_CKTX0_EN_FORCE_EN | > > DA_CKM_BIAS_LPF_EN_FORCE_VAL | > > + DA_CKM_BIAS_EN_FORCE_VAL | > > + DA_XTP_GLB_LDO_EN_FORCE_VAL | > > + DA_XTP_GLB_AVD10_ON_FORCE_VAL); > > + > > + if (ret) > > + return ret; > > + > > + /* Disable RX */ > > + ret = mtk_dp_write(mtk_dp, MTK_DP_1040, 0); > > > MTK_DP_1040 is defined as: > > +#define MTK_DP_1040 (BIT(6) | BIT(12)) > > I think this a weird address. > > Regards, > CK > Hello CK, I will change them to 0x34 and 0x1040. BRs, Rex > > + > > + if (ret) > > + return ret; > > + > > + ret = mtk_dp_write(mtk_dp, MTK_DP_TOP_MEM_PD, > > + 0x550 | BIT(FUSE_SEL_SHIFT) | > > BIT(MEM_ISO_EN_SHIFT)); > > + > > + return ret; > > +} > >