From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Rajendra Nayak <quic_rjendra@quicinc.com>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Georgi Djakov <djakov@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Thara Gopinath <thara.gopinath@gmail.com>
Subject: Re: [PATCH v5 4/4] arm64: dts: qcom: sdm845: Add CPU BWMON
Date: Wed, 29 Jun 2022 13:32:02 +0200 [thread overview]
Message-ID: <479a021a-36eb-7b44-9e14-51e16d1b64fb@linaro.org> (raw)
In-Reply-To: <87b83a0c-0ea2-6839-1d90-8f1145ed9ed2@quicinc.com>
On 29/06/2022 13:22, Rajendra Nayak wrote:
>
>
> On 6/29/2022 1:22 PM, Krzysztof Kozlowski wrote:
>> Add device node for CPU-memory BWMON device (bandwidth monitoring) on
>> SDM845 measuring bandwidth between CPU (gladiator_noc) and Last Level
>> Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth
>> votes from cpufreq (CPU nodes) thus achieve high memory throughput even
>> with lower CPU frequencies.
>>
>> Co-developed-by: Thara Gopinath <thara.gopinath@gmail.com>
>> Signed-off-by: Thara Gopinath <thara.gopinath@gmail.com>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 38 ++++++++++++++++++++++++++++
>> 1 file changed, 38 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> index 83e8b63f0910..e0f088996390 100644
>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> @@ -2026,6 +2026,44 @@ llcc: system-cache-controller@1100000 {
>> interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
>> };
>>
>> + pmu@1436400 {
>> + compatible = "qcom,sdm845-cpu-bwmon", "qcom,msm8998-cpu-bwmon";
>> + reg = <0 0x01436400 0 0x600>;
>> + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
>> + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
>> +
>> + operating-points-v2 = <&cpu_bwmon_opp_table>;
>> +
>> + cpu_bwmon_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + /*
>> + * The interconnect paths bandwidths taken from
>> + * cpu4_opp_table bandwidth.
>> + * They also match different tables from
>> + * msm-4.9 downstream kernel:
>> + * - the OSM L3 from bandwidth table of
>> + * qcom,cpu4-l3lat-mon (qcom,core-dev-table);
>> + * bus width: 16 bytes;
>> + */
>
> Maybe the comment needs an update?
Yes, a bit.
Best regards,
Krzysztof
prev parent reply other threads:[~2022-06-29 11:32 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-29 7:52 [PATCH v5 0/4] soc/arm64: qcom: Add initial version of bwmon Krzysztof Kozlowski
2022-06-29 7:52 ` [PATCH v5 1/4] dt-bindings: interconnect: qcom,msm8998-cpu-bwmon: add BWMON device Krzysztof Kozlowski
2022-06-29 11:21 ` Rajendra Nayak
2022-06-29 11:22 ` Krzysztof Kozlowski
2022-06-30 14:26 ` Bjorn Andersson
2022-06-29 7:52 ` [PATCH v5 2/4] soc: qcom: icc-bwmon: Add bandwidth monitoring driver Krzysztof Kozlowski
2022-06-29 7:52 ` [PATCH v5 3/4] arm64: defconfig: enable Qualcomm Bandwidth Monitor Krzysztof Kozlowski
2022-06-29 7:52 ` [PATCH v5 4/4] arm64: dts: qcom: sdm845: Add CPU BWMON Krzysztof Kozlowski
2022-06-29 11:22 ` Rajendra Nayak
2022-06-29 11:32 ` Krzysztof Kozlowski [this message]
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