From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34E22C4727C for ; Wed, 30 Sep 2020 16:34:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E661B2072E for ; Wed, 30 Sep 2020 16:34:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725815AbgI3QeO (ORCPT ); Wed, 30 Sep 2020 12:34:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725355AbgI3QeO (ORCPT ); Wed, 30 Sep 2020 12:34:14 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 033B8C061755 for ; Wed, 30 Sep 2020 09:34:14 -0700 (PDT) Received: from [2a0a:edc0:0:900:6245:cbff:fea0:1793] (helo=kresse.office.stw.pengutronix.de) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1kNf3Q-00052K-6s; Wed, 30 Sep 2020 18:34:09 +0200 Message-ID: <502fb976959b61472be351576ca8e6c880bea2bf.camel@pengutronix.de> From: Lucas Stach To: Marek Vasut , Shawn Guo , Rob Herring Cc: devicetree@vger.kernel.org, Frieder Schrempf , patchwork-lst@pengutronix.de, NXP Linux Team , kernel@pengutronix.de, Fabio Estevam , linux-arm-kernel@lists.infradead.org Date: Wed, 30 Sep 2020 18:34:07 +0200 In-Reply-To: References: <20200930155006.535712-1-l.stach@pengutronix.de> <20200930155006.535712-8-l.stach@pengutronix.de> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.5-1.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:6245:cbff:fea0:1793 X-SA-Exim-Mail-From: l.stach@pengutronix.de Subject: Re: [PATCH 07/11] soc: imx: gpcv2: add support for optional resets X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mi, 2020-09-30 at 18:30 +0200, Marek Vasut wrote: > On 9/30/20 6:23 PM, Lucas Stach wrote: > > On Mi, 2020-09-30 at 18:15 +0200, Marek Vasut wrote: > > > On 9/30/20 5:50 PM, Lucas Stach wrote: > > > > Normally the reset for the devices inside the power domain is > > > > triggered automatically from the PGC in the power-up sequencing, > > > > however on i.MX8MM this doesn't work for the GPU power domains. > > > > > > One has to wonder whether the VPU power domain has similar hardware bug > > > on the MX8MM ? > > > > Nope the VPUs have separate reset bits in the BLK_CTL. So after > > powering up the VPUMIX domain one can assert/deassert reset to the > > individual VPU cores. > > Is there any documentation for the BLK_CTL on MX8MM ? I can't find any > in the official RM. I'm still waiting on some info from NXP about this. It is not documented in the RM. > And also, the GPUs need to use SRC reset, does the BLK_CTL reset do the > same "degree" of reset to the VPU as the SRC reset does to the GPUs ? At least that is what I'm assuming. The fundamental issue with the GPU domain is that there is no BLK_CTL in the GPUMIX domain and the resets are hooked up to the shared SRC reset, instead of having GPU BLK_CTL level resets. Regards, Lucas