From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Rob Herring <robh+dt@kernel.org>,
Damien Le Moal <damien.lemoal@wdc.com>,
Lewis Hanly <lewis.hanly@microchip.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Conor Dooley <conor.dooley@microchip.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Geert Uytterhoeven <geert@linux-m68k.org>
Subject: [PATCH v2 07/11] riscv: dts: microchip: mpfs: Group tuples in interrupt properties
Date: Thu, 16 Dec 2021 14:37:31 +0100 [thread overview]
Message-ID: <5920780dc81102ff11a5521d9476249141fca36b.1639660956.git.geert@linux-m68k.org> (raw)
In-Reply-To: <cover.1639660956.git.geert@linux-m68k.org>
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.
Fix this by grouping the tuples of "interrupts" and
"interrupts-extended" properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v2:
- Add Reviewed-by.
---
.../boot/dts/microchip/microchip-mpfs.dtsi | 31 ++++++++++---------
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index d9c1dee3fb25beb8..869aaf0d5c066c9d 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -158,18 +158,18 @@ cache-controller@2010000 {
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic>;
- interrupts = <1 2 3>;
+ interrupts = <1>, <2>, <3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7
- &cpu2_intc 3 &cpu2_intc 7
- &cpu3_intc 3 &cpu3_intc 7
- &cpu4_intc 3 &cpu4_intc 7>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>;
};
plic: interrupt-controller@c000000 {
@@ -178,11 +178,11 @@ plic: interrupt-controller@c000000 {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
- interrupts-extended = <&cpu0_intc 11
- &cpu1_intc 11 &cpu1_intc 9
- &cpu2_intc 11 &cpu2_intc 9
- &cpu3_intc 11 &cpu3_intc 9
- &cpu4_intc 11 &cpu4_intc 9>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>;
riscv,ndev = <186>;
};
@@ -190,7 +190,8 @@ dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
- interrupts = <23 24 25 26 27 28 29 30>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>;
#dma-cells = <1>;
};
@@ -254,7 +255,7 @@ mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
- interrupts = <88 89>;
+ interrupts = <88>, <89>;
clocks = <&clkcfg 6>;
max-frequency = <200000000>;
status = "disabled";
@@ -264,7 +265,7 @@ emac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
interrupt-parent = <&plic>;
- interrupts = <64 65 66 67>;
+ interrupts = <64>, <65>, <66>, <67>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg 4>, <&clkcfg 2>;
clock-names = "pclk", "hclk";
@@ -277,7 +278,7 @@ emac1: ethernet@20112000 {
compatible = "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
interrupt-parent = <&plic>;
- interrupts = <70 71 72 73>;
+ interrupts = <70>, <71>, <72>, <73>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg 5>, <&clkcfg 2>;
status = "disabled";
--
2.25.1
next prev parent reply other threads:[~2021-12-16 13:37 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
2021-12-08 10:40 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Biju Das
2021-12-08 10:40 ` [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support Biju Das
2021-12-10 14:44 ` Biju Das
2021-12-14 19:21 ` Rob Herring
2021-12-14 19:31 ` Biju Das
2021-12-13 16:46 ` Steven Price
2021-12-14 19:25 ` Rob Herring
2021-12-08 10:40 ` [PATCH v3 2/3] arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node Biju Das
2021-12-08 10:40 ` [PATCH v3 3/3] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator Biju Das
2021-12-16 13:46 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Geert Uytterhoeven
2021-12-16 13:47 ` Geert Uytterhoeven
2021-12-16 13:47 ` Geert Uytterhoeven
2021-12-16 14:00 ` Daniel Stone
2021-12-16 14:02 ` Biju Das
2021-12-15 15:46 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Miquel Raynal
2021-12-15 15:46 ` [PATCH v4 1/4] dt-bindings: mtd: rzn1: Describe Renesas RZ/N1 NAND controller Miquel Raynal
2021-12-16 20:23 ` Rob Herring
2021-12-15 15:46 ` [PATCH v4 2/4] mtd: rawnand: rzn1: Add new NAND controller driver Miquel Raynal
2021-12-15 15:46 ` [PATCH v4 3/4] MAINTAINERS: Add an entry for Renesas RZ/N1 NAND controller Miquel Raynal
2021-12-15 15:46 ` [PATCH v4 4/4] ARM: dts: r9a06g032: Describe " Miquel Raynal
2021-12-16 9:13 ` Geert Uytterhoeven
2021-12-16 13:47 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Geert Uytterhoeven
2021-12-16 13:48 ` Geert Uytterhoeven
2021-12-16 13:48 ` Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 01/11] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 02/11] riscv: dts: canaan: Group tuples in interrupt properties Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 03/11] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 04/11] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 05/11] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven
2021-12-16 14:39 ` Conor.Dooley
2021-12-16 13:37 ` [PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node Geert Uytterhoeven
2021-12-16 14:47 ` Conor.Dooley
2021-12-16 13:37 ` Geert Uytterhoeven [this message]
2021-12-16 13:37 ` [PATCH v2 08/11] riscv: dts: sifive: Group tuples in interrupt properties Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 09/11] riscv: dts: sifive: Group tuples in register properties Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 10/11] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 11/11] riscv: dts: sifive: fu540-c000: Fix PLIC node Geert Uytterhoeven
2021-12-16 13:41 [PATCH v2 0/2] dt-bindings: interrupt-controller: sifive,plic: Miscellaneous improvements Geert Uytterhoeven
2021-12-16 13:41 ` [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Fix number of interrupts Geert Uytterhoeven
2021-12-16 21:29 ` Rob Herring
2021-12-16 13:41 ` [PATCH v2 2/2] dt-bindings: interrupt-controller: sifive,plic: Group interrupt tuples Geert Uytterhoeven
2021-12-16 21:29 ` Rob Herring
2021-12-16 21:28 ` [PATCH v2 0/2] dt-bindings: interrupt-controller: sifive,plic: Miscellaneous improvements Rob Herring
2021-12-17 8:02 ` Geert Uytterhoeven
2021-12-16 13:43 [PATCH v2 0/2] dt-bindings: timer: sifive,clint: " Geert Uytterhoeven
2021-12-16 13:43 ` [PATCH v2 1/2] dt-bindings: timer: sifive,clint: Fix number of interrupts Geert Uytterhoeven
2021-12-16 21:30 ` Rob Herring
2021-12-16 13:43 ` [PATCH v2 2/2] dt-bindings: timer: sifive,clint: Group interrupt tuples Geert Uytterhoeven
2021-12-16 21:30 ` Rob Herring
2021-12-20 12:20 ` [PATCH v2 0/2] dt-bindings: timer: sifive,clint: Miscellaneous improvements Daniel Lezcano
2021-12-20 12:22 ` Daniel Lezcano
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