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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id v17sm9118533wrr.60.2020.09.10.06.46.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Sep 2020 06:46:51 -0700 (PDT) Subject: Re: [PATCH] ARM: zynq: Add Z-turn board V5 To: agriveaux@deutnet.info, michal.simek@xilinx.com, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20200909150608.1984952-1-agriveaux@deutnet.info> From: Michal Simek Autocrypt: addr=monstr@monstr.eu; keydata= xsFNBFFuvDEBEAC9Amu3nk79+J+4xBOuM5XmDmljuukOc6mKB5bBYOa4SrWJZTjeGRf52VMc howHe8Y9nSbG92obZMqsdt+d/hmRu3fgwRYiiU97YJjUkCN5paHXyBb+3IdrLNGt8I7C9RMy svSoH4WcApYNqvB3rcMtJIna+HUhx8xOk+XCfyKJDnrSuKgx0Svj446qgM5fe7RyFOlGX/wF Ae63Hs0RkFo3I/+hLLJP6kwPnOEo3lkvzm3FMMy0D9VxT9e6Y3afe1UTQuhkg8PbABxhowzj SEnl0ICoqpBqqROV/w1fOlPrm4WSNlZJunYV4gTEustZf8j9FWncn3QzRhnQOSuzTPFbsbH5 WVxwDvgHLRTmBuMw1sqvCc7CofjsD1XM9bP3HOBwCxKaTyOxbPJh3D4AdD1u+cF/lj9Fj255 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oa0OZXydlVP7wrnJdi3m8DnljxyInPxbxdKGN5XnMq/r9Y70uRVyeqwp97sKLXd9GsxuaSg7 QJKUaltvN/i7ng1UOT/xsKeVdfXuqDIIElZ+dyEVTweDM011Zv0NN3OWFz6oD+GzyBetuBwD 0Z1MQlmNcq2bhOMzTxuXX2NDzUZs4aqEyZQ= Message-ID: <5e0bf2ca-307e-f610-95c4-441864293a7a@monstr.eu> Date: Thu, 10 Sep 2020 15:46:51 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20200909150608.1984952-1-agriveaux@deutnet.info> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 09. 09. 20 17:06, agriveaux@deutnet.info wrote: > From: Alexandre GRIVEAUX > > Adding Z-turn board V5 to resolve the change between: > > "Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035 > "Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031 > > At this time the S25FL128SAGNFI003 doesn't work because of bug: > > *** Warning - spi_flash_probe_bus_cs() failed, using default environment > > Signed-off-by: Alexandre GRIVEAUX > --- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/zynq-zturn-v5.dts | 121 ++++++++ > .../xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c | 273 ++++++++++++++++++ > configs/xilinx_zynq_virt_defconfig | 4 +- > 4 files changed, 398 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/zynq-zturn-v5.dts > create mode 100644 board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index f8f529435b..0f8973b1c8 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -277,6 +277,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ > zynq-zc770-xm013.dtb \ > zynq-zed.dtb \ > zynq-zturn.dtb \ > + zynq-zturn-v5.dtb \ > zynq-zybo.dtb \ > zynq-zybo-z7.dtb > dtb-$(CONFIG_ARCH_ZYNQMP) += \ > diff --git a/arch/arm/dts/zynq-zturn-v5.dts b/arch/arm/dts/zynq-zturn-v5.dts > new file mode 100644 > index 0000000000..eebeec800f > --- /dev/null > +++ b/arch/arm/dts/zynq-zturn-v5.dts > @@ -0,0 +1,121 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020 Alexandre Griveaux > + * > + * Based on zynq-zturn.dts which is: > + * Copyright (C) 2015 Andrea Merello > + * Copyright (C) 2017 Alexander Graf > + * > + */ > + > +/dts-v1/; > +/include/ "zynq-7000.dtsi" > + > +/ { > + model = "Zynq Z-Turn MYIR Board V5"; > + compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; > + > + aliases { > + ethernet0 = &gem0; > + serial0 = &uart1; > + serial1 = &uart0; > + mmc0 = &sdhci0; > + }; > + > + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x40000000>; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + gpio-leds { > + compatible = "gpio-leds"; > + usr-led1 { > + label = "usr-led1"; > + gpios = <&gpio0 0x0 0x1>; > + default-state = "off"; > + }; > + > + usr-led2 { > + label = "usr-led2"; > + gpios = <&gpio0 0x9 0x1>; > + default-state = "off"; > + }; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + autorepeat; > + K1 { > + label = "K1"; > + gpios = <&gpio0 0x32 0x1>; > + linux,code = <0x66>; > + wakeup-source; > + autorepeat; > + }; > + }; > +}; > + > +&clkc { > + ps-clk-frequency = <33333333>; > +}; > + > +&qspi { > + u-boot,dm-pre-reloc; > + status = "okay"; > +}; > + > +&gem0 { > + status = "okay"; > + phy-mode = "rgmii-id"; > + phy-handle = <ðernet_phy>; > + > + ethernet_phy: ethernet-phy@0 { > + reg = <0x3>; > + }; > +}; > + > +&sdhci0 { > + u-boot,dm-pre-reloc; > + status = "okay"; > +}; > + > +&uart0 { > + u-boot,dm-pre-reloc; > + status = "okay"; > +}; > + > +&uart1 { > + u-boot,dm-pre-reloc; > + status = "okay"; > +}; > + > +&usb0 { > + status = "okay"; > + dr_mode = "host"; > +}; > + > +&can0 { > + status = "okay"; > +}; > + > +&i2c0 { > + status = "okay"; > + clock-frequency = <400000>; > + > + stlm75@49 { > + status = "okay"; > + compatible = "lm75"; > + reg = <0x49>; > + }; > + > + accelerometer@53 { > + compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; > + reg = <0x53>; > + interrupt-parent = <&intc>; > + interrupts = <0x0 0x1e 0x4>; > + }; > +}; > diff --git a/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c > new file mode 100644 > index 0000000000..5d573868cb > --- /dev/null > +++ b/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c > @@ -0,0 +1,273 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) Xilinx, Inc. > + */ > + > +#include > + > +static unsigned long ps7_pll_init_data[] = { > + EMIT_WRITE(0xF8000008, 0x0000DF0DU), > + EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U), > + EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U), > + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U), > + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U), > + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U), > + EMIT_MASKPOLL(0xF800010C, 0x00000001U), > + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U), > + EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U), > + EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U), > + EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U), > + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U), > + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U), > + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U), > + EMIT_MASKPOLL(0xF800010C, 0x00000002U), > + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U), > + EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U), > + EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U), > + EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U), > + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U), > + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U), > + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U), > + EMIT_MASKPOLL(0xF800010C, 0x00000004U), > + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U), > + EMIT_WRITE(0xF8000004, 0x0000767BU), > + EMIT_EXIT(), > +}; > + > +static unsigned long ps7_clock_init_data[] = { > + EMIT_WRITE(0xF8000008, 0x0000DF0DU), > + EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U), > + EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U), > + EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U), > + EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U), > + EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U), > + EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A03U), > + EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00200501U), > + EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U), > + EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U), > + EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U), > + EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00400500U), > + EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), > + EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FD044DU), > + EMIT_WRITE(0xF8000004, 0x0000767BU), > + EMIT_EXIT(), > +}; > + > +static unsigned long ps7_ddr_init_data[] = { > + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U), > + EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001082U), > + EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU), > + EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U), > + EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U), > + EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004285BU), > + EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D3U), > + EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x7282BCE5U), > + EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U), > + EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U), > + EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U), > + EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U), > + EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040B30U), > + EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U), > + EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U), > + EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U), > + EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U), > + EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U), > + EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U), > + EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U), > + EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U), > + EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U), > + EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU), > + EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U), > + EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U), > + EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U), > + EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U), > + EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U), > + EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U), > + EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U), > + EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU), > + EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), > + EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U), > + EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U), > + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U), > + EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U), > + EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U), > + EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U), > + EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U), > + EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U), > + EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U), > + EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U), > + EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U), > + EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U), > + EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0002A81FU), > + EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029822U), > + EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C10U), > + EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00026013U), > + EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U), > + EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U), > + EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U), > + EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U), > + EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009FU), > + EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U), > + EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000090U), > + EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000093U), > + EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000FFU), > + EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000FBU), > + EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U), > + EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000EDU), > + EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DFU), > + EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U), > + EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000D0U), > + EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000D3U), > + EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U), > + EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U), > + EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U), > + EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU), > + EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU), > + EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU), > + EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU), > + EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU), > + EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU), > + EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU), > + EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU), > + EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U), > + EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U), > + EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U), > + EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U), > + EMIT_MASKPOLL(0xF8000B74, 0x00002000U), > + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U), > + EMIT_MASKPOLL(0xF8006054, 0x00000007U), > + EMIT_EXIT(), > +}; > + > +static unsigned long ps7_mio_init_data[] = { > + EMIT_WRITE(0xF8000008, 0x0000DF0DU), > + EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U), > + EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U), > + EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U), > + EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U), > + EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U), > + EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U), > + EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U), > + EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), > + EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU), > + EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU), > + EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU), > + EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U), > + EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U), > + EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U), > + EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U), > + EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U), > + EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00000602U), > + EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U), > + EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U), > + EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U), > + EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U), > + EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U), > + EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U), > + EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U), > + EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000600U), > + EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000016E1U), > + EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000016E0U), > + EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001640U), > + EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001640U), > + EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001621U), > + EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001620U), > + EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U), > + EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U), > + EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U), > + EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U), > + EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U), > + EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U), > + EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U), > + EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U), > + EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U), > + EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U), > + EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U), > + EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U), > + EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U), > + EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U), > + EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U), > + EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U), > + EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U), > + EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U), > + EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U), > + EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U), > + EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U), > + EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U), > + EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U), > + EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U), > + EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U), > + EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U), > + EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U), > + EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U), > + EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U), > + EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U), > + EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00000201U), > + EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00000201U), > + EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U), > + EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U), > + EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U), > + EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U), > + EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U), > + EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U), > + EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU), > + EMIT_WRITE(0xF8000004, 0x0000767BU), > + EMIT_EXIT(), > +}; > + > +static unsigned long ps7_peripherals_init_data[] = { > + EMIT_WRITE(0xF8000008, 0x0000DF0DU), > + EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U), > + EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U), > + EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), > + EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), > + EMIT_WRITE(0xF8000004, 0x0000767BU), > + EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), > + EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), > + EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U), > + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U), > + EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00080000U), > + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370000U), > + EMIT_MASKDELAY(0xF8F00200, 1), > + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U), > + EMIT_EXIT(), > +}; > + > +static unsigned long ps7_post_config_0[] = { > + EMIT_WRITE(0xF8000008, 0x0000DF0DU), > + EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU), > + EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U), > + EMIT_WRITE(0xF8000004, 0x0000767BU), > + EMIT_EXIT(), > +}; > + > +int ps7_post_config(void) > +{ > + return ps7_config(ps7_post_config_0); > +} > + > +int ps7_init(void) > +{ > + int ret; > + > + ret = ps7_config(ps7_mio_init_data); > + if (ret != PS7_INIT_SUCCESS) > + return ret; > + > + ret = ps7_config(ps7_pll_init_data); > + if (ret != PS7_INIT_SUCCESS) > + return ret; > + > + ret = ps7_config(ps7_clock_init_data); > + if (ret != PS7_INIT_SUCCESS) > + return ret; > + > + ret = ps7_config(ps7_ddr_init_data); > + if (ret != PS7_INIT_SUCCESS) > + return ret; > + > + ret = ps7_config(ps7_peripherals_init_data); > + if (ret != PS7_INIT_SUCCESS) > + return ret; > + return PS7_INIT_SUCCESS; > +} > diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig > index 8acdab25b7..afbc81afd1 100644 > --- a/configs/xilinx_zynq_virt_defconfig > +++ b/configs/xilinx_zynq_virt_defconfig > @@ -49,7 +49,7 @@ CONFIG_CMD_MTDPARTS=y > CONFIG_CMD_MTDPARTS_SPREAD=y > CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y > CONFIG_CMD_UBI=y > -CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0" > +CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zturn-v5 zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0" > CONFIG_ENV_OVERWRITE=y > CONFIG_ENV_IS_IN_SPI_FLASH=y > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > @@ -90,6 +90,8 @@ CONFIG_SPI_FLASH_WINBOND=y > CONFIG_PHY_MARVELL=y > CONFIG_PHY_REALTEK=y > CONFIG_PHY_XILINX=y > +CONFIG_PHY_MICREL=y > +CONFIG_PHY_MICREL_KSZ90X1=y > CONFIG_MII=y > CONFIG_ZYNQ_GEM=y > CONFIG_ARM_DCC=y > As I wrote to u-boot mailing list. I prefer to make this simpler because the most of that stuff is just c&p. What about this? #include "zynq-zturn.dts"; / { model = "Zynq Z-Turn MYIR Board V5"; compatible = "myir,zynq-zturn-v5", "myir,zynq-zturn", "xlnx,zynq-7000"; }; ðernet_phy { reg = <3>; }; Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs