From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11F1ECCA47B for ; Fri, 10 Jun 2022 02:27:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242784AbiFJC1t (ORCPT ); Thu, 9 Jun 2022 22:27:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230148AbiFJC1s (ORCPT ); Thu, 9 Jun 2022 22:27:48 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D0DC20F6A; Thu, 9 Jun 2022 19:27:46 -0700 (PDT) X-UUID: fdd1cd53a01c4c63a3a38c63bbf374fa-20220610 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:4b4a4b28-ab7f-4874-8397-f6c0cc69a2ab,OB:0,LO B:0,IP:0,URL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:25 X-CID-META: VersionHash:2a19b09,CLOUDID:4a12de7e-c8dc-403a-96e8-6237210dceee,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:0,BEC:nil X-UUID: fdd1cd53a01c4c63a3a38c63bbf374fa-20220610 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 851581953; Fri, 10 Jun 2022 10:27:43 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 10 Jun 2022 10:27:41 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 10 Jun 2022 10:27:41 +0800 Message-ID: <602b51beaa91390ea3f4a0a6e47623708283d255.camel@mediatek.com> Subject: Re: [PATCH v10 02/21] dt-bindings: mediatek,dp: Add Display Port binding From: Rex-BC Chen To: Chunfeng Yun , Guillaume Ranquet , Chun-Kuang Hu , "Philipp Zabel" , David Airlie , "Daniel Vetter" , Rob Herring , "Krzysztof Kozlowski" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Kishon Vijay Abraham I , "Vinod Koul" , Helge Deller , CK Hu , Jitao shi CC: Markus Schneider-Pargmann , , , , , , , Date: Fri, 10 Jun 2022 10:27:41 +0800 In-Reply-To: <1998a59df3b27fbeb0ca7945925e47336977bcd5.camel@mediatek.com> References: <20220523104758.29531-1-granquet@baylibre.com> <20220523104758.29531-3-granquet@baylibre.com> <1998a59df3b27fbeb0ca7945925e47336977bcd5.camel@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, 2022-05-24 at 11:35 +0800, Chunfeng Yun wrote: > On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote: > > From: Markus Schneider-Pargmann > > > > This controller is present on several mediatek hardware. Currently > > mt8195 and mt8395 have this controller without a functional > > difference, > > so only one compatible field is added. > > > > The controller can have two forms, as a normal display port and as > > an > > embedded display port. > > > > Signed-off-by: Markus Schneider-Pargmann > > Signed-off-by: Guillaume Ranquet > > --- > > .../display/mediatek/mediatek,dp.yaml | 99 > > +++++++++++++++++++ > > 1 file changed, 99 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > ml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > ml > > new file mode 100644 > > index 000000000000..36ae0a6df299 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > ml > > @@ -0,0 +1,99 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek Display Port Controller > > + > > +maintainers: > > + - CK Hu > > + - Jitao shi > > + > > +description: | > > + Device tree bindings for the MediaTek (embedded) Display Port > > controller > > + present on some MediaTek SoCs. > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt8195-dp-tx > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: faxi clock > > + > > + clock-names: > > + items: > > + - const: faxi > > + > > + power-domains: > > + maxItems: 1 > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: Input endpoint of the controller, usually > > dp_intf > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: Output endpoint of the controller > > + > > + max-lanes: > > + maxItems: 1 > > + description: maximum number of lanes supported by the hardware > > + > > + max-linkrate: > > + maxItems: 1 > > + description: maximum link rate supported by the hardware > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - ports > > + - max-lanes > > + - max-linkrate > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + #include > > + edp_tx: edp_tx@1c500000 { > > 'edp_tx: ' can be removed > Hello Chunfeng, ok, I will drop it. > > + compatible = "mediatek,mt8195-dp-tx"; > > + reg = <0 0x1c500000 0 0x8000>; > > reg = <0x1c500000 0x8000>; > #address-cells, #size-cells are both 1 by default > I will use "eg = <0x1c500000 0x8000>;" in binding example. BRs, Bo-Chen > > + interrupts = ; > > + power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&edp_pin>; > > + max-lanes = /bits/ 8 <4>; > > + max-linkrate = /bits/ 8 <0x1e>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + edp_in: endpoint { > > + remote-endpoint = <&dp_intf0_out>; > > + }; > > + }; > > + port@1 { > > + reg = <1>; > > + edp_out: endpoint { > > + remote-endpoint = <&panel_in>; > > + }; > > + }; > > + }; > > + };