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From: Sylwester Nawrocki <s.nawrocki@samsung.com>
To: Chanwoo Choi <cw00.choi@samsung.com>
Cc: georgi.djakov@linaro.org, krzk@kernel.org,
	devicetree@vger.kernel.org, robh+dt@kernel.org,
	a.swigon@samsung.com, myungjoo.ham@samsung.com,
	inki.dae@samsung.com, sw0312.kim@samsung.com,
	b.zolnierkie@samsung.com, m.szyprowski@samsung.com,
	linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v7 2/6] interconnect: Add generic interconnect driver for Exynos SoCs
Date: Tue, 3 Nov 2020 12:32:33 +0100	[thread overview]
Message-ID: <6cc9a2f8-9d9a-68b7-9f47-e16fefb18d88@samsung.com> (raw)
In-Reply-To: <88af4e53-6c7a-c2e6-ad28-a9d6bb5bf623@samsung.com>

On 03.11.2020 10:37, Chanwoo Choi wrote:
> On 10/30/20 9:51 PM, Sylwester Nawrocki wrote:
>> This patch adds a generic interconnect driver for Exynos SoCs in order
>> to provide interconnect functionality for each "samsung,exynos-bus"
>> compatible device.
>>
>> The SoC topology is a graph (or more specifically, a tree) and its
>> edges are specified using the 'samsung,interconnect-parent' in the
> 
> samsung,interconnect-parent -> interconnects?

Yes, I will rephrase the whole commit message as it's a bit outdated now.

I've changed the sentence to:
"The SoC topology is a graph (or more specifically, a tree) and its
edges are described by specifying in the 'interconnects' property
the interconnect consumer path for each interconnect provider DT node."

>> DT. Due to unspecified relative probing order, -EPROBE_DEFER may be
>> propagated to ensure that the parent is probed before its children.
>>
>> Each bus is now an interconnect provider and an interconnect node as
>> well (cf. Documentation/interconnect/interconnect.rst), i.e. every bus
>> registers itself as a node. Node IDs are not hardcoded but rather
>> assigned dynamically at runtime. This approach allows for using this
>> driver with various Exynos SoCs.
>>
>> Frequencies requested via the interconnect API for a given node are
>> propagated to devfreq using dev_pm_qos_update_request(). Please note
>> that it is not an error when CONFIG_INTERCONNECT is 'n', in which
>> case all interconnect API functions are no-op.
>>
>> The bus-width DT property is to determine the interconnect data
>> width and traslate requested bandwidth to clock frequency for each
>> bus.
>>
>> Signed-off-by: Artur Świgoń <a.swigon@samsung.com>
>> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

>> +++ b/drivers/interconnect/exynos/exynos.c

>> +struct exynos_icc_priv {
>> +	struct device *dev;
>> +
>> +	/* One interconnect node per provider */
>> +	struct icc_provider provider;
>> +	struct icc_node *node;
>> +
>> +	struct dev_pm_qos_request qos_req;
>> +	u32 bus_clk_ratio;
>> +};
>> +
>> +static struct icc_node *exynos_icc_get_parent(struct device_node *np)
>> +{
>> +	struct of_phandle_args args;
>> +	struct icc_node_data *icc_node_data;
>> +	struct icc_node *icc_node;
>> +	int num, ret;
>> +
>> +	num = of_count_phandle_with_args(np, "interconnects",
>> +					 "#interconnect-cells");
>> +	if (num < 1)
>> +		return NULL; /* parent nodes are optional */
>> +
>> +	/* Get the interconnect target node */
>> +	ret = of_parse_phandle_with_args(np, "interconnects",
>> +					"#interconnect-cells", 0, &args);
>> +	if (ret < 0)
>> +		return ERR_PTR(ret);
>> +
>> +	icc_node_data = of_icc_get_from_provider(&args);
>> +	of_node_put(args.np);
>> +
>> +	if (IS_ERR(icc_node_data))
>> +		return ERR_CAST(icc_node_data);
>> +
>> +	icc_node = icc_node_data->node;
>> +	kfree(icc_node_data);
>> +
>> +	return icc_node;
>> +}
> 
> I have a question about exynos_icc_get_parent().
> As I checked, this function returns the only one icc_node
> as parent node. But, bus_display dt node in the exynos4412.dtsi
> specifies the two interconnect node as following with bus_leftbus, bus_dmc,
> 
> When I checked the return value of exynos_icc_get_parent()
> during probing for bus_display device, exynos_icc_get_parent() function
> only returns 'bus_leftbus' icc_node. Do you need to add two phandle
> of icc node?

Yes, as we use the interconnect consumer bindings we need to specify a path,
i.e. a <initiator, target> pair. When the provider node initializes it will
link itself to that path. Currently the provider driver uses just the first 
phandle.

> +++ b/arch/arm/boot/dts/exynos4412.dtsi
> @@ -472,7 +472,7 @@
>                         clocks = <&clock CLK_ACLK160>;
>                         clock-names = "bus";
>                         operating-points-v2 = <&bus_display_opp_table>;
>                         interconnects = <&bus_leftbus &bus_dmc>;
>                         #interconnect-cells = <0>;
>                         status = "disabled";
>                 };

-- 
Regards,
Sylwester

  reply	other threads:[~2020-11-03 11:33 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20201030125221eucas1p14e525f75c4b8dadae04144ce7684d776@eucas1p1.samsung.com>
2020-10-30 12:51 ` [PATCH v7 0/6] Exynos: Simple QoS for exynos-bus using interconnect Sylwester Nawrocki
     [not found]   ` <CGME20201030125257eucas1p29c6b018cfcdda337b2b3d2a496f0c830@eucas1p2.samsung.com>
2020-10-30 12:51     ` [PATCH v7 1/6] dt-bindings: devfreq: Add documentation for the interconnect properties Sylwester Nawrocki
2020-10-31 12:12       ` Krzysztof Kozlowski
2020-11-03  9:40       ` Chanwoo Choi
     [not found]   ` <CGME20201030125301eucas1p218b0e654cb4c826b05280f28836da8d9@eucas1p2.samsung.com>
2020-10-30 12:51     ` [PATCH v7 2/6] interconnect: Add generic interconnect driver for Exynos SoCs Sylwester Nawrocki
2020-10-31 12:17       ` Krzysztof Kozlowski
2020-11-02 12:23         ` Sylwester Nawrocki
2020-11-03  8:11       ` Georgi Djakov
2020-11-03  9:37       ` Chanwoo Choi
2020-11-03 11:32         ` Sylwester Nawrocki [this message]
2020-11-03 14:12           ` Chanwoo Choi
2020-11-03 17:30             ` Sylwester Nawrocki
     [not found]   ` <CGME20201030125303eucas1p14a9de4111ffafc1870527abdea0994c9@eucas1p1.samsung.com>
2020-10-30 12:51     ` [PATCH v7 3/6] PM / devfreq: exynos-bus: Add registration of interconnect child device Sylwester Nawrocki
2020-10-31 12:40       ` Krzysztof Kozlowski
2020-11-02  4:28       ` Chanwoo Choi
2020-11-03 10:45       ` Chanwoo Choi
2020-11-03 12:32         ` Sylwester Nawrocki
2020-11-03 13:11           ` Krzysztof Kozlowski
2020-11-03 14:07           ` Chanwoo Choi
     [not found]   ` <CGME20201030125305eucas1p2d61ba397d77a72e0d1dce8d30b278e16@eucas1p2.samsung.com>
2020-10-30 12:51     ` [PATCH v7 4/6] ARM: dts: exynos: Add interconnect properties to Exynos4412 bus nodes Sylwester Nawrocki
     [not found]   ` <CGME20201030125307eucas1p14afc8cc8828f2bc838e769b77d7e9c95@eucas1p1.samsung.com>
2020-10-30 12:51     ` [PATCH v7 5/6] ARM: dts: exynos: Add interconnects to Exynos4412 mixer Sylwester Nawrocki
     [not found]   ` <CGME20201030125308eucas1p14ae969ae1d5549d422c478aa54d3311e@eucas1p1.samsung.com>
2020-10-30 12:51     ` [PATCH v7 6/6] drm: exynos: mixer: Add interconnect support Sylwester Nawrocki
2020-10-31 12:44       ` Krzysztof Kozlowski
2020-10-31 12:47       ` Krzysztof Kozlowski
2020-11-02 12:40         ` Sylwester Nawrocki
2020-11-03  7:54   ` [PATCH v7 0/6] Exynos: Simple QoS for exynos-bus using interconnect Chanwoo Choi
2020-11-03  8:29     ` Georgi Djakov
2020-11-03  8:53       ` Chanwoo Choi
2020-11-03 10:12         ` Sylwester Nawrocki
2020-11-03 10:37           ` Chanwoo Choi

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