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listexpand id S1728358AbgEUKZ2 (ORCPT ); Thu, 21 May 2020 06:25:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727009AbgEUKZ1 (ORCPT ); Thu, 21 May 2020 06:25:27 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EE9AC061A0E; Thu, 21 May 2020 03:25:26 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id n5so5840583wmd.0; Thu, 21 May 2020 03:25:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:cc:references:from:autocrypt:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=GffMNgQRsIRxtQq2pj6h0TutYxk1IVYKcYTeNXIC640=; b=L9+l3YHxWGnFHJDEQaO8FgD5mey6YNp+6FYRnc/J/z8ZdnUVWfbURuAeQz5lC1OVCR UQxWMdT8YJYQYR6/tccEfZdpHHhcqMl7+DdpZdOxLy2vpeX4pjmaupV8+DO89d3kxT10 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ABdhPJwGd4f0Xr0dKJxEkRC3mz+5c9kwW1cIcYnYO25Q+7zMm42Z5nAY9Z7u53b4YK0ftmyWqy5jKg== X-Received: by 2002:a1c:4b0e:: with SMTP id y14mr8740159wma.170.1590056724830; Thu, 21 May 2020 03:25:24 -0700 (PDT) Received: from ziggy.stardust ([213.195.113.243]) by smtp.gmail.com with ESMTPSA id s11sm5900101wrp.79.2020.05.21.03.25.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 May 2020 03:25:24 -0700 (PDT) Subject: Re: [PATCH V3] arm64: dts: mediatek: add cpufreq and cci devfreq nodes for mt8183 To: "Andrew-sh.Cheng" , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, srv_heupstream@mediatek.com References: <1576826785-3867-1-git-send-email-andrew-sh.cheng@mediatek.com> From: Matthias Brugger Autocrypt: addr=matthias.bgg@gmail.com; prefer-encrypt=mutual; keydata= mQINBFP1zgUBEAC21D6hk7//0kOmsUrE3eZ55kjc9DmFPKIz6l4NggqwQjBNRHIMh04BbCMY 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XUSrUUTRimTkuMHrTYaHY3544a+GduQQLLA+avseLmjvKHxsU4zna0p0Yb4czwoJj+wSkVGQ NMDbxcY26CMPK204jhRm9RG687qq6691hbiuAtWABeAsl1AS+mdS7aP/4uOM4kFCvXYgIHxP /BoVz9CZTMEVAZVzbRKyYCLUf1wLhcHzugTiONz9fWMBLLskKvq7m1tlr61mNgY9nVwwClMU uE7i1H9r/2/UXLd+pY82zcXhFrfmKuCDmOkB5xPsOMVQJH8I0/lbqfLAqfsxSb/X1VKaP243 jzi+DzD9cvj2K6eD5j5kcKJJQactXqfJvF1Eb+OnxlB1BCLE8D1rNkPO5O742Mq3MgDmq19l +abzEL6QDAAxn9md8KwrA3RtucNh87cHlDXfUBKa7SRvBjTczDg+HEPNk2u3hrz1j3l2rliQ y1UfYx7Vk/TrdwUIJgKS8QAr8Lw9WuvY2hSqL9vEjx8VAkPWNWPwrQ== Message-ID: <753e91a6-6765-ee3a-462f-d07f60af2de9@gmail.com> Date: Thu, 21 May 2020 12:25:22 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <1576826785-3867-1-git-send-email-andrew-sh.cheng@mediatek.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 20/12/2019 08:26, Andrew-sh.Cheng wrote: > From: "Andrew-sh.Cheng" > > add cpufreq and cci devfreq nodes for mt8183 > > Depend on regulator node patch: > https://patchwork.kernel.org/patch/11284617/ > > Signed-off-by: Andrew-sh.Cheng > --- Now queued for v5.7-next/dts64 Thanks! > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 36 ++++ > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 245 ++++++++++++++++++++++++++++ > 2 files changed, 281 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > index 1fb195c..ca5c0b2 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > @@ -231,6 +231,42 @@ > > }; > > +&cci { > + proc-supply = <&mt6358_vproc12_reg>; > +}; > + > +&cpu0 { > + proc-supply = <&mt6358_vproc12_reg>; > +}; > + > +&cpu1 { > + proc-supply = <&mt6358_vproc12_reg>; > +}; > + > +&cpu2 { > + proc-supply = <&mt6358_vproc12_reg>; > +}; > + > +&cpu3 { > + proc-supply = <&mt6358_vproc12_reg>; > +}; > + > +&cpu4 { > + proc-supply = <&mt6358_vproc11_reg>; > +}; > + > +&cpu5 { > + proc-supply = <&mt6358_vproc11_reg>; > +}; > + > +&cpu6 { > + proc-supply = <&mt6358_vproc11_reg>; > +}; > + > +&cpu7 { > + proc-supply = <&mt6358_vproc11_reg>; > +}; > + > &uart0 { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 10b3247..d260a5a 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -31,6 +31,219 @@ > i2c11 = &i2c11; > }; > > + cluster0_opp: opp_table0 { > + compatible = "operating-points-v2"; > + opp-shared; > + opp00 { > + opp-hz = /bits/ 64 <793000000>; > + opp-microvolt = <650000>; > + }; > + opp01 { > + opp-hz = /bits/ 64 <910000000>; > + opp-microvolt = <687500>; > + }; > + opp02 { > + opp-hz = /bits/ 64 <1014000000>; > + opp-microvolt = <718750>; > + }; > + opp03 { > + opp-hz = /bits/ 64 <1131000000>; > + opp-microvolt = <756250>; > + }; > + opp04 { > + opp-hz = /bits/ 64 <1248000000>; > + opp-microvolt = <800000>; > + }; > + opp05 { > + opp-hz = /bits/ 64 <1326000000>; > + opp-microvolt = <818750>; > + }; > + opp06 { > + opp-hz = /bits/ 64 <1417000000>; > + opp-microvolt = <850000>; > + }; > + opp07 { > + opp-hz = /bits/ 64 <1508000000>; > + opp-microvolt = <868750>; > + }; > + opp08 { > + opp-hz = /bits/ 64 <1586000000>; > + opp-microvolt = <893750>; > + }; > + opp09 { > + opp-hz = /bits/ 64 <1625000000>; > + opp-microvolt = <906250>; > + }; > + opp10 { > + opp-hz = /bits/ 64 <1677000000>; > + opp-microvolt = <931250>; > + }; > + opp11 { > + opp-hz = /bits/ 64 <1716000000>; > + opp-microvolt = <943750>; > + }; > + opp12 { > + opp-hz = /bits/ 64 <1781000000>; > + opp-microvolt = <975000>; > + }; > + opp13 { > + opp-hz = /bits/ 64 <1846000000>; > + opp-microvolt = <1000000>; > + }; > + opp14 { > + opp-hz = /bits/ 64 <1924000000>; > + opp-microvolt = <1025000>; > + }; > + opp15 { > + opp-hz = /bits/ 64 <1989000000>; > + opp-microvolt = <1050000>; > + }; }; > + > + cluster1_opp: opp_table1 { > + compatible = "operating-points-v2"; > + opp-shared; > + opp00 { > + opp-hz = /bits/ 64 <793000000>; > + opp-microvolt = <700000>; > + }; > + opp01 { > + opp-hz = /bits/ 64 <910000000>; > + opp-microvolt = <725000>; > + }; > + opp02 { > + opp-hz = /bits/ 64 <1014000000>; > + opp-microvolt = <750000>; > + }; > + opp03 { > + opp-hz = /bits/ 64 <1131000000>; > + opp-microvolt = <775000>; > + }; > + opp04 { > + opp-hz = /bits/ 64 <1248000000>; > + opp-microvolt = <800000>; > + }; > + opp05 { > + opp-hz = /bits/ 64 <1326000000>; > + opp-microvolt = <825000>; > + }; > + opp06 { > + opp-hz = /bits/ 64 <1417000000>; > + opp-microvolt = <850000>; > + }; > + opp07 { > + opp-hz = /bits/ 64 <1508000000>; > + opp-microvolt = <875000>; > + }; > + opp08 { > + opp-hz = /bits/ 64 <1586000000>; > + opp-microvolt = <900000>; > + }; > + opp09 { > + opp-hz = /bits/ 64 <1625000000>; > + opp-microvolt = <912500>; > + }; > + opp10 { > + opp-hz = /bits/ 64 <1677000000>; > + opp-microvolt = <931250>; > + }; > + opp11 { > + opp-hz = /bits/ 64 <1716000000>; > + opp-microvolt = <950000>; > + }; > + opp12 { > + opp-hz = /bits/ 64 <1781000000>; > + opp-microvolt = <975000>; > + }; > + opp13 { > + opp-hz = /bits/ 64 <1846000000>; > + opp-microvolt = <1000000>; > + }; > + opp14 { > + opp-hz = /bits/ 64 <1924000000>; > + opp-microvolt = <1025000>; > + }; > + opp15 { > + opp-hz = /bits/ 64 <1989000000>; > + opp-microvolt = <1050000>; > + }; > + }; > + > + cci_opp: opp_table2 { > + compatible = "operating-points-v2"; > + opp-shared; > + opp00 { > + opp-hz = /bits/ 64 <273000000>; > + opp-microvolt = <650000>; > + }; > + opp01 { > + opp-hz = /bits/ 64 <338000000>; > + opp-microvolt = <687500>; > + }; > + opp02 { > + opp-hz = /bits/ 64 <403000000>; > + opp-microvolt = <718750>; > + }; > + opp03 { > + opp-hz = /bits/ 64 <463000000>; > + opp-microvolt = <756250>; > + }; > + opp04 { > + opp-hz = /bits/ 64 <546000000>; > + opp-microvolt = <800000>; > + }; > + opp05 { > + opp-hz = /bits/ 64 <624000000>; > + opp-microvolt = <818750>; > + }; > + opp06 { > + opp-hz = /bits/ 64 <689000000>; > + opp-microvolt = <850000>; > + }; > + opp07 { > + opp-hz = /bits/ 64 <767000000>; > + opp-microvolt = <868750>; > + }; > + opp08 { > + opp-hz = /bits/ 64 <845000000>; > + opp-microvolt = <893750>; > + }; > + opp09 { > + opp-hz = /bits/ 64 <871000000>; > + opp-microvolt = <906250>; > + }; > + opp10 { > + opp-hz = /bits/ 64 <923000000>; > + opp-microvolt = <931250>; > + }; > + opp11 { > + opp-hz = /bits/ 64 <962000000>; > + opp-microvolt = <943750>; > + }; > + opp12 { > + opp-hz = /bits/ 64 <1027000000>; > + opp-microvolt = <975000>; > + }; > + opp13 { > + opp-hz = /bits/ 64 <1092000000>; > + opp-microvolt = <1000000>; > + }; > + opp14 { > + opp-hz = /bits/ 64 <1144000000>; > + opp-microvolt = <1025000>; > + }; > + opp15 { > + opp-hz = /bits/ 64 <1196000000>; > + opp-microvolt = <1050000>; > + }; > + }; > + > + cci: cci { > + compatible = "mediatek,mt8183-cci"; > + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>; > + clock-names = "cci_clock"; > + operating-points-v2 = <&cci_opp>; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -73,6 +286,10 @@ > reg = <0x000>; > enable-method = "psci"; > capacity-dmips-mhz = <741>; > + clocks = <&mcucfg CLK_MCU_MP0_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu1: cpu@1 { > @@ -81,6 +298,10 @@ > reg = <0x001>; > enable-method = "psci"; > capacity-dmips-mhz = <741>; > + clocks = <&mcucfg CLK_MCU_MP0_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu2: cpu@2 { > @@ -89,6 +310,10 @@ > reg = <0x002>; > enable-method = "psci"; > capacity-dmips-mhz = <741>; > + clocks = <&mcucfg CLK_MCU_MP0_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu3: cpu@3 { > @@ -97,6 +322,10 @@ > reg = <0x003>; > enable-method = "psci"; > capacity-dmips-mhz = <741>; > + clocks = <&mcucfg CLK_MCU_MP0_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu4: cpu@100 { > @@ -105,6 +334,10 @@ > reg = <0x100>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > + clocks = <&mcucfg CLK_MCU_MP2_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster1_opp>; > }; > > cpu5: cpu@101 { > @@ -113,6 +346,10 @@ > reg = <0x101>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > + clocks = <&mcucfg CLK_MCU_MP2_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster1_opp>; > }; > > cpu6: cpu@102 { > @@ -121,6 +358,10 @@ > reg = <0x102>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > + clocks = <&mcucfg CLK_MCU_MP2_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster1_opp>; > }; > > cpu7: cpu@103 { > @@ -129,6 +370,10 @@ > reg = <0x103>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > + clocks = <&mcucfg CLK_MCU_MP2_SEL>, > + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cluster1_opp>; > }; > }; > >