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Subject: Re: [PATCH 2/3] dt-bindings: phy: Add lane<n>-mode property to WIZ
 (SERDES wrapper)
To:     Jyri Sarha <jsarha@ti.com>, Rob Herring <robh@kernel.org>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        <devicetree@vger.kernel.org>,
        Tomi Valkeinen <tomi.valkeinen@ti.com>,
        Praneeth Bajjuri <praneeth@ti.com>,
        Yuti Amonkar <yamonkar@cadence.com>,
        Swapnil Kashinath Jakhade <sjakhade@cadence.com>,
        Roger Quadros <rogerq@ti.com>
References: <cover.1575906694.git.jsarha@ti.com>
 <fb79923b1591cc5f26b6973beb92ce503ad3f4d1.1575906694.git.jsarha@ti.com>
 <20191219190833.GA16358@bogus> <3cf64e30-6b4d-a138-7164-54d1cdc8e05a@ti.com>
 <CAL_JsqKNFbPebM=pC+GL_DMuf5OPZF4FyJ7KGdSonDAeL_3P1A@mail.gmail.com>
 <15d0bd42-5bb5-ee14-9e2a-7beb55671e8a@ti.com>
From:   Kishon Vijay Abraham I <kishon@ti.com>
Message-ID: <763b3a26-98bd-25c2-687b-e644c5bcb05b@ti.com>
Date:   Mon, 30 Dec 2019 15:48:34 +0530
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Hi,

On 30/12/19 3:07 PM, Jyri Sarha wrote:
> On 24/12/2019 23:31, Rob Herring wrote:
>> On Fri, Dec 20, 2019 at 5:52 AM Jyri Sarha <jsarha@ti.com> wrote:
>>>
>>> On 19/12/2019 21:08, Rob Herring wrote:
>>>> On Mon, Dec 09, 2019 at 06:22:11PM +0200, Jyri Sarha wrote:
>>>>> Add property to indicate the usage of SERDES lane controlled by the
>>>>> WIZ wrapper. The wrapper configuration has some variation depending on
>>>>> how each lane is going to be used.
>>>>>
>>>>> Signed-off-by: Jyri Sarha <jsarha@ti.com>
>>>>> ---
>>>>>  .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml    | 12 ++++++++++++
>>>>>  1 file changed, 12 insertions(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
>>>>> index 94e3b4b5ed8e..399725f65278 100644
>>>>> --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
>>>>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
>>>>> @@ -97,6 +97,18 @@ patternProperties:
>>>>>        Torrent SERDES should follow the bindings specified in
>>>>>        Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
>>>>>
>>>>> +  "^lane[1-4]-mode$":
>>>>> +    allOf:
>>>>> +      - $ref: /schemas/types.yaml#/definitions/uint32
>>>>> +      - enum: [0, 1, 2, 3, 4, 5, 6]
>>>>> +    description: |
>>>>> +     Integer describing static lane usage for the lane indicated in
>>>>> +     the property name. For Sierra there may be properties lane0 and
>>>>> +     lane1, for Torrent all lane[1-4]-mode properties may be
>>>>> +     there. The constants to indicate the lane usage are defined in
>>>>> +     "include/dt-bindings/phy/phy.h". The lane is assumed to be unused
>>>>> +     if its lane<n>-use property does not exist.
>>>>
>>>> The defines were intended to be in 'phys' cells. Does putting both lane
>>>> and mode in the client 'phys' properties not work?
>>>>
>>>
>>> Let me first check if I understood you. So you are suggesting something
>>> like this:
>>>
>>> dp-phy {
>>>         #phy-cells = <5>; /* 1 for phy-type and 4 for lanes = 5 */
>>>         ...
>>> };
>>>
>>> dp-bridge {
>>>         ...
>>>         phys = <&dp-phy PHY_TYPE_DP 1 1 0 0>; /* lanes 0 and 1 for DP */
>>
>> Yes, but I think the lanes can be a single cell mask. And I'd probably
>> make that the first cell which is generally "which PHY" and make
>> type/mode the 2nd cell. I'd look for other users of PHY_TYPE_ defines
>> and match what they've done if possible.
>>
> 
> I see. This will cause some head ache on the driver implementation side,
> as there is no way for the phy driver to peek the lane use or type from
> the phy client's device tree node. It also looks to me that the phy
> API[1] has to be extended quite a bit before the phy client can pass the
> lane usage information to the phy driver. It will cause some pain to
> implement the extension without breaking the phy API and causing a nasty
> cross dependency over all the phy client domains.
> 
> Also, there is not much point in putting the PHY_TYPE constant to the
> phy client's node, as normally the phy client driver will know quite
> well what PHY_TYPE to use. E.g. a SATA driver will always select
> PHY_TYPE_SATA and a PCIE driver will select PHY_TYPE_PCIE, etc.
> 
> Kishon, if we have to take this road it also starts to sound like we
> will have to move the phy client's phandle to point to the phy wrapper
> node, if we want to keep the actual phy driver wrapper agnostic. Then we
> can make the wrapper to act like a proxy that forwards the phy_ops calls
> to the actual phy driver. Luckily the per lane phy-type selection is not
> a blocker for our j721e DisplayPort functionality.

WIZ is a PHY wrapper and not a PHY in itself. I'm not inclined in
modeling WIZ as a PHY and adding an additional level of indirection.
This can add more challenges w.r.t PHY sequencing and can also lead to
locking issues. That also doesn't accurately represent the HW bock.

Thanks
Kishon