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Sat, 7 Aug 2021 05:25:53 +0000 Received: from [172.17.173.69] (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 7 Aug 2021 05:25:53 +0000 Subject: Re: [RFC 03/11] hte: Add tegra194 HTE kernel provider To: Kent Gibson CC: , , , , , , , , , References: <20210625235532.19575-1-dipenp@nvidia.com> <20210625235532.19575-4-dipenp@nvidia.com> <20210701142156.GA34285@sol> <52768891-6c01-7588-e557-5c9eae5375b6@nvidia.com> <20210731154323.GA24906@sol> <1ff6df66-9895-bd42-322a-515327f30366@nvidia.com> <20210807030746.GA9850@sol> <91a173b3-18dc-5d6b-002f-893e7478717b@nvidia.com> <20210807045116.GA13675@sol> X-Nvconfidentiality: public From: Dipen Patel Message-ID: <7f6a2591-c264-e005-18ae-242320d4a22e@nvidia.com> Date: Fri, 6 Aug 2021 22:35:10 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210807045116.GA13675@sol> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 26735bb9-1de6-402e-8bc2-08d95963d38e X-MS-TrafficTypeDiagnostic: BY5PR12MB5526: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2021 05:25:53.4445 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 26735bb9-1de6-402e-8bc2-08d95963d38e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB5526 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 8/6/21 9:51 PM, Kent Gibson wrote: > On Fri, Aug 06, 2021 at 09:52:54PM -0700, Dipen Patel wrote: >> On 8/6/21 8:07 PM, Kent Gibson wrote: >>> On Fri, Aug 06, 2021 at 07:41:09PM -0700, Dipen Patel wrote: >>>> On 7/31/21 8:43 AM, Kent Gibson wrote: >>>>> On Wed, Jul 28, 2021 at 04:59:08PM -0700, Dipen Patel wrote: >>>>>> Thanks Kent for the review comment. My responses inline. >>>>>> > > >>>> 2. Does hte handler solution create race between two handlers? i.e. edge_irq_handler and >>>> >>>> hte_handler, for the worst case scenario as below? >>>> >>> No. If hardware timestamp is selected then no irq is requested from the >>> irq subsystem for that line - only from the hte subsystem instead. >>> So there will be no edge_irq_handler call for that line, so no possible race. >> That is not possible for certain providers, for example the one I am dealing >> >> with which requires GPIO line to be requested as input and IRQ needs to >> >> be enabled on them. >> > So, for your hte subsystem to work, the consumer has to also request > a line from the irq subsystem? Yes > That makes sense to you? Its not me, its peculiarity of the hardware that I am dealing with. > Have hte do that, rather than the consumer. Sure, for cdev it would mean to duplicate (most of) the edge* or line_create code in HTE. For such hardware, my initial doubt remains the same about the worst case scenario between two handlers, but perhaps that's implementation details for hte to handle. > > And another reason it makes sense to integrate this with irq... Alright, will explore this route as well. I remember both Thierry[1] and Marc[2] raised some doubts (time to revive that discussion). [1]: https://lore.kernel.org/lkml/YFm9r%2FtFkzVlYDEp@orome.fritz.box/ [2]: https://lore.kernel.org/lkml/87h7l1k9yi.wl-maz@kernel.org/ > > Cheers, > Kent.