From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15E41C43334 for ; Thu, 30 Jun 2022 09:12:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232859AbiF3JMz convert rfc822-to-8bit (ORCPT ); Thu, 30 Jun 2022 05:12:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233291AbiF3JMy (ORCPT ); Thu, 30 Jun 2022 05:12:54 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46C101CFE8 for ; Thu, 30 Jun 2022 02:12:50 -0700 (PDT) Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1o6qDn-0002b6-SL; Thu, 30 Jun 2022 11:12:23 +0200 Received: from [2a0a:edc0:0:900:1d::4e] (helo=lupine) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1o6qDh-003YyD-6B; Thu, 30 Jun 2022 11:12:20 +0200 Received: from pza by lupine with local (Exim 4.94.2) (envelope-from ) id 1o6qDk-0003Cl-3a; Thu, 30 Jun 2022 11:12:20 +0200 Message-ID: <813a3b51f82a11a86bd3af2c3299c344e08e8963.camel@pengutronix.de> Subject: Re: [PATCH v1 04/14] reset: add polarfire soc reset support From: Philipp Zabel To: Conor Dooley , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Palmer Dabbelt , Nicolas Ferre , Claudiu Beznea , Daire McNamara Cc: Paul Walmsley , Albert Ou , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org Date: Thu, 30 Jun 2022 11:12:20 +0200 In-Reply-To: <20220630080532.323731-5-conor.dooley@microchip.com> References: <20220630080532.323731-1-conor.dooley@microchip.com> <20220630080532.323731-5-conor.dooley@microchip.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT User-Agent: Evolution 3.38.3-1 MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Conor, On Do, 2022-06-30 at 09:05 +0100, Conor Dooley wrote: Add support for the resets on Microchip's PolarFire SoC (MPFS). Reset control is a single register, wedged in between registers for clock control. To fit with existed DT etc, the reset controller is existing ^ created using the aux device framework & set up in the clock driver. Signed-off-by: Conor Dooley ---  drivers/reset/Kconfig | 9 +++  drivers/reset/Makefile | 2 +-  drivers/reset/reset-mpfs.c | 145 +++++++++++++++++++++++++++++++++++++  3 files changed, 155 insertions(+), 1 deletion(-)  create mode 100644 drivers/reset/reset-mpfs.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 93c8d07ee328..edf48951f763 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -122,6 +122,15 @@ config RESET_MCHP_SPARX5   help   This driver supports switch core reset for the Microchip Sparx5 SoC.   +config RESET_POLARFIRE_SOC + bool "Microchip PolarFire SoC (MPFS) Reset Driver" + depends on AUXILIARY_BUS && MCHP_CLK_MPFS + default MCHP_CLK_MPFS + help + This driver supports peripheral reset for the Microchip PolarFire SoC + + CONFIG_RESET_MPFS This doesn't look intentional. +  config RESET_MESON   tristate "Meson Reset Driver"   depends on ARCH_MESON || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index a80a9c4008a7..5fac3a753858 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_RESET_K210) += reset-k210.o  obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o  obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o  obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o +obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o  obj-$(CONFIG_RESET_MESON) += reset-meson.o  obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o  obj-$(CONFIG_RESET_NPCM) += reset-npcm.o @@ -38,4 +39,3 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o  obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o  obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o  obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o - diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c new file mode 100644 index 000000000000..49c47a3e6c70 --- /dev/null +++ b/drivers/reset/reset-mpfs.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PolarFire SoC (MPFS) Peripheral Clock Reset Controller + * + * Author: Conor Dooley + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + */ +#include +#include +#include +#include +#include +#include +#include + +/* + * The ENVM reset is the lowest bit in the register & I am using the CLK_FOO + * defines in the dt to make things easier to configure - so this is accounting + * for the offset of 3 there. + */ +#define MPFS_PERIPH_OFFSET CLK_ENVM +#define MPFS_NUM_RESETS 30u +#define MPFS_SLEEP_MIN_US 100 +#define MPFS_SLEEP_MAX_US 200 + +/* + * Peripheral clock resets + */ + +static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + u32 reg; + + reg = mpfs_reset_read(rcdev->dev); + reg |= (1u << id); + mpfs_reset_write(rcdev->dev, reg); This is missing a spinlock to protect against concurrent read-modify- writes. + + return 0; +} + +static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + u32 reg, val; + + reg = mpfs_reset_read(rcdev->dev); + val = reg & ~(1u << id); You could use BIT(id) instead of (1u << id). + mpfs_reset_write(rcdev->dev, val); + + return 0; +} + +static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + u32 reg = mpfs_reset_read(rcdev->dev); + + return (reg & (1u << id)); Side note, this works because MPFS_NUM_RESETS makes sure the sign bit is never hit. +} + +static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + mpfs_assert(rcdev, id); + + usleep_range(MPFS_SLEEP_MIN_US, MPFS_SLEEP_MAX_US); + + mpfs_deassert(rcdev, id); + + return 0; +} + +static const struct reset_control_ops mpfs_reset_ops = { + .reset = mpfs_reset, + .assert = mpfs_assert, + .deassert = mpfs_deassert, + .status = mpfs_status, +}; + +static int mpfs_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned int index = reset_spec->args[0]; + + /* + * CLK_RESERVED does not map to a clock, but it does map to a reset, + * so it has to be accounted for here. It is the reset for the fabric, + * so if this reset gets called - do not reset it. + */ + if (index == CLK_RESERVED) { + dev_err(rcdev->dev, "Resetting the fabric is not supported\n"); + return -EINVAL; + } + + if (index < MPFS_PERIPH_OFFSET || index >= (MPFS_PERIPH_OFFSET + rcdev->nr_resets)) { + dev_err(rcdev->dev, "Invalid reset index %u\n", reset_spec->args[0]); s/reset_spec->args[0]/index/ + return -EINVAL; + } + + return index - MPFS_PERIPH_OFFSET; +} + +static int mpfs_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev = &adev->dev; + struct reset_controller_dev *rcdev; + int ret; + + rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL); + if (!rcdev) + return -ENOMEM; + + rcdev->dev = dev; + rcdev->dev->parent = adev->dev.parent; s/adev->dev./dev->/ + rcdev->ops = &mpfs_reset_ops; + rcdev->of_node = adev->dev.parent->of_node; s/adev->dev./dev->/ + rcdev->of_reset_n_cells = 1; + rcdev->of_xlate = mpfs_reset_xlate; + rcdev->nr_resets = MPFS_NUM_RESETS; + + ret = devm_reset_controller_register(dev, rcdev); + if (!ret) + dev_info(dev, "Registered MPFS reset controller\n"); Is this really useful information for most users? + + return ret; +} + +static const struct auxiliary_device_id mpfs_reset_ids[] = { + { + .name = "clk_mpfs.reset-mpfs", + }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); + +static struct auxiliary_driver mpfs_reset_driver = { + .probe = mpfs_reset_probe, + .id_table = mpfs_reset_ids, +}; + +module_auxiliary_driver(mpfs_reset_driver); + +MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(MCHP_CLK_MPFS); regards Philipp