From mboxrd@z Thu Jan  1 00:00:00 1970
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Subject: Re: [PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree
Date: Fri, 17 Jun 2016 02:14:50 +0000
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Cc: Geert Uytterhoeven <geert@linux-m68k.org>, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>, Simon Horman <horms@verge.net.au>, "open list:MEDIA DRIVERS FOR RENESAS - FCP" <linux-renesas-soc@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Kumar Gala <galak@codeaurora.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, Magnus Damm <magnus.damm@gmail.com>, Russell King <linux@arm.linux.org.uk>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>
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Hi Geert

> > Right, I had forgotten about that.
> > Fortunately the clk-rcar-gen2 driver has a sane failure mode for this case ;-)
> > 
> > it seems the RCAN clock can just be modeled as a fixed clock. However,
> > its divider value isn't clear to me, as 15.9 MHz cannot be generated from PLL1
> > using an integer divider. Morimoto-san, can you please ask for clarification?
> 
> OK.
> Now, I asked to HW team about that.
> Please wait.

RCAN divider is fixed for 1/49

PLL1 (= 1560MHz) 
  -> 1/2 (= 780MHz)
    -> RCAN divider 1/49 (= 15.9183..MHz)

Is this clear for you ?