From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78A18C4320A for ; Wed, 4 Aug 2021 15:05:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E2336104F for ; Wed, 4 Aug 2021 15:05:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231272AbhHDPFn (ORCPT ); Wed, 4 Aug 2021 11:05:43 -0400 Received: from mail.kernel.org ([198.145.29.99]:37494 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237601AbhHDPFk (ORCPT ); Wed, 4 Aug 2021 11:05:40 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 318D560F0F; Wed, 4 Aug 2021 15:05:28 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mBISU-002wco-BN; Wed, 04 Aug 2021 16:05:26 +0100 Date: Wed, 04 Aug 2021 16:05:25 +0100 Message-ID: <87im0lw8qy.wl-maz@kernel.org> From: Marc Zyngier To: Kishon Vijay Abraham I Cc: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Tom Joseph , , , , , , Lokesh Vutla Subject: Re: [PATCH v2 1/3] dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts In-Reply-To: <20210804132912.30685-2-kishon@ti.com> References: <20210804132912.30685-1-kishon@ti.com> <20210804132912.30685-2-kishon@ti.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kishon@ti.com, bhelgaas@google.com, robh+dt@kernel.org, lorenzo.pieralisi@arm.com, tjoseph@cadence.com, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lokeshvutla@ti.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, 04 Aug 2021 14:29:10 +0100, Kishon Vijay Abraham I wrote: > > Add bindings to specify interrupt controller for legacy interrupts. > > Signed-off-by: Kishon Vijay Abraham I > --- > .../bindings/pci/ti,j721e-pci-host.yaml | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > index cc900202df29..f461d7b4c0cc 100644 > --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > @@ -74,6 +74,11 @@ properties: > > msi-map: true > > +patternProperties: > + "interrupt-controller": > + type: object > + description: interrupt controller to handle legacy interrupts. > + > required: > - compatible > - reg > @@ -97,6 +102,8 @@ unevaluatedProperties: false > > examples: > - | > + #include > + #include > #include > #include > > @@ -131,5 +138,13 @@ examples: > ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>, > <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>; > dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; > + > + > + pcie0_intc: interrupt-controller { > + interrupt-controller; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic500>; > + interrupts = ; Are you sure about the edge signalling? How is the interrupt retriggered when the input is still high, which could well be the case for shared INTx? Thanks, M. -- Without deviation from the norm, progress is not possible.